b572b5f821
- pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJUd7jIAAoJEPOmecmc0R2BrOkIAJpMe0tqHxtcN1fBSS2rS3/b bgcu37WfGXt1FkBkGPyoVfy0m6tQ9hHx07o62IowVvaWzmvoQppLmC20+y6gKVMj nVGlhbfhZ3bDJBbsbWAyzQvH+fJx+pOTIGQJCCNX/aixSYnfvda/FP0u7EVrY4W/ mF/b5mPmHhah9EeyuAwy4eAT5xCCER5DqR9eryObDwj3N9cUluM9BiK1JWXXWdYt i/p3NS+MEjFG2KrLB+Rzu39yFRsjF8IOBKuYNh752NVcsNy2CuxqbDSpn8NM2niW bxW07X5J8JSpecpuzJmkuOomauE+4pKXMM3W+XL+XO8iF3h9inXXp0nzX31cQRI= =st2A -----END PGP SIGNATURE----- Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next - clock phase setting capability for the rk3288 mmc clocks - pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers |
||
|---|---|---|
| .. | ||
| clk-cpu.c | ||
| clk-mmc-phase.c | ||
| clk-pll.c | ||
| clk-rk3188.c | ||
| clk-rk3288.c | ||
| clk-rockchip.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| softrst.c | ||