345 lines
8.8 KiB
C
345 lines
8.8 KiB
C
/*
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* (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
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*
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* Parts of this file were based on sources as follows:
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*
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* Copyright (c) 2006-2008 Intel Corporation
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* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
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* Copyright (C) 2011 Texas Instruments
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms of
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* such GNU licence.
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*
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*/
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#include <linux/amba/clcd-regs.h>
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#include <linux/clk.h>
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#include <linux/version.h>
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#include <linux/dma-buf.h>
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#include <linux/of_graph.h>
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#include <drm/drmP.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include "pl111_drm.h"
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irqreturn_t pl111_irq(int irq, void *data)
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{
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struct pl111_drm_dev_private *priv = data;
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u32 irq_stat;
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irqreturn_t status = IRQ_NONE;
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irq_stat = readl(priv->regs + CLCD_PL111_MIS);
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if (!irq_stat)
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return IRQ_NONE;
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if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
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drm_crtc_handle_vblank(&priv->pipe.crtc);
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status = IRQ_HANDLED;
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}
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/* Clear the interrupt once done */
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writel(irq_stat, priv->regs + CLCD_PL111_ICR);
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return status;
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}
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static u32 pl111_get_fb_offset(struct drm_plane_state *pstate)
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{
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struct drm_framebuffer *fb = pstate->fb;
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struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
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return (obj->paddr +
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fb->offsets[0] +
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fb->format->cpp[0] * pstate->src_x +
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fb->pitches[0] * pstate->src_y);
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}
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static int pl111_display_check(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *pstate,
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struct drm_crtc_state *cstate)
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{
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const struct drm_display_mode *mode = &cstate->mode;
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struct drm_framebuffer *old_fb = pipe->plane.state->fb;
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struct drm_framebuffer *fb = pstate->fb;
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if (mode->hdisplay % 16)
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return -EINVAL;
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if (fb) {
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u32 offset = pl111_get_fb_offset(pstate);
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/* FB base address must be dword aligned. */
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if (offset & 3)
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return -EINVAL;
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/* There's no pitch register -- the mode's hdisplay
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* controls it.
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*/
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if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
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return -EINVAL;
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/* We can't change the FB format in a flicker-free
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* manner (and only update it during CRTC enable).
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*/
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if (old_fb && old_fb->format != fb->format)
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cstate->mode_changed = true;
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}
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return 0;
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}
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static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
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struct drm_crtc_state *cstate)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_plane *plane = &pipe->plane;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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const struct drm_display_mode *mode = &cstate->mode;
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struct drm_framebuffer *fb = plane->state->fb;
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struct drm_connector *connector = &priv->connector.connector;
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u32 cntl;
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u32 ppl, hsw, hfp, hbp;
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u32 lpp, vsw, vfp, vbp;
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u32 cpl;
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int ret;
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ret = clk_set_rate(priv->clk, mode->clock * 1000);
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if (ret) {
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dev_err(drm->dev,
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"Failed to set pixel clock rate to %d: %d\n",
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mode->clock * 1000, ret);
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}
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clk_prepare_enable(priv->clk);
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ppl = (mode->hdisplay / 16) - 1;
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hsw = mode->hsync_end - mode->hsync_start - 1;
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hfp = mode->hsync_start - mode->hdisplay - 1;
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hbp = mode->htotal - mode->hsync_end - 1;
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lpp = mode->vdisplay - 1;
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vsw = mode->vsync_end - mode->vsync_start - 1;
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vfp = mode->vsync_start - mode->vdisplay;
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vbp = mode->vtotal - mode->vsync_end;
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cpl = mode->hdisplay - 1;
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writel((ppl << 2) |
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(hsw << 8) |
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(hfp << 16) |
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(hbp << 24),
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priv->regs + CLCD_TIM0);
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writel(lpp |
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(vsw << 10) |
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(vfp << 16) |
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(vbp << 24),
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priv->regs + CLCD_TIM1);
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/* XXX: We currently always use CLCDCLK with no divisor. We
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* could probably reduce power consumption by using HCLK
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* (apb_pclk) with a divisor when it gets us near our target
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* pixel clock.
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*/
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writel(((mode->flags & DRM_MODE_FLAG_NHSYNC) ? TIM2_IHS : 0) |
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((mode->flags & DRM_MODE_FLAG_NVSYNC) ? TIM2_IVS : 0) |
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((connector->display_info.bus_flags &
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DRM_BUS_FLAG_DE_LOW) ? TIM2_IOE : 0) |
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((connector->display_info.bus_flags &
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DRM_BUS_FLAG_PIXDATA_NEGEDGE) ? TIM2_IPC : 0) |
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TIM2_BCD |
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(cpl << 16),
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priv->regs + CLCD_TIM2);
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writel(0, priv->regs + CLCD_TIM3);
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drm_panel_prepare(priv->connector.panel);
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/* Enable and Power Up */
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cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDPWR | CNTL_LCDVCOMP(1);
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/* Note that the the hardware's format reader takes 'r' from
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* the low bit, while DRM formats list channels from high bit
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* to low bit as you read left to right.
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*/
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switch (fb->format->format) {
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_XBGR8888:
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cntl |= CNTL_LCDBPP24;
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break;
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XRGB8888:
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cntl |= CNTL_LCDBPP24 | CNTL_BGR;
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break;
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case DRM_FORMAT_BGR565:
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cntl |= CNTL_LCDBPP16_565;
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break;
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case DRM_FORMAT_RGB565:
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cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
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break;
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_XBGR1555:
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cntl |= CNTL_LCDBPP16;
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break;
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_XRGB1555:
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cntl |= CNTL_LCDBPP16 | CNTL_BGR;
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break;
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case DRM_FORMAT_ABGR4444:
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case DRM_FORMAT_XBGR4444:
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cntl |= CNTL_LCDBPP16_444;
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break;
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case DRM_FORMAT_ARGB4444:
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case DRM_FORMAT_XRGB4444:
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cntl |= CNTL_LCDBPP16_444 | CNTL_BGR;
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break;
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default:
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WARN_ONCE(true, "Unknown FB format 0x%08x\n",
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fb->format->format);
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break;
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}
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writel(cntl, priv->regs + CLCD_PL111_CNTL);
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drm_panel_enable(priv->connector.panel);
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drm_crtc_vblank_on(crtc);
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}
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void pl111_display_disable(struct drm_simple_display_pipe *pipe)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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drm_crtc_vblank_off(crtc);
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drm_panel_disable(priv->connector.panel);
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/* Disable and Power Down */
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writel(0, priv->regs + CLCD_PL111_CNTL);
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drm_panel_unprepare(priv->connector.panel);
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clk_disable_unprepare(priv->clk);
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}
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static void pl111_display_update(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *old_pstate)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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struct drm_pending_vblank_event *event = crtc->state->event;
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struct drm_plane *plane = &pipe->plane;
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struct drm_plane_state *pstate = plane->state;
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struct drm_framebuffer *fb = pstate->fb;
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if (fb) {
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u32 addr = pl111_get_fb_offset(pstate);
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writel(addr, priv->regs + CLCD_UBAS);
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}
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if (event) {
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crtc->state->event = NULL;
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spin_lock_irq(&crtc->dev->event_lock);
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if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
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drm_crtc_arm_vblank_event(crtc, event);
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else
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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}
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int pl111_enable_vblank(struct drm_device *drm, unsigned int crtc)
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{
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struct pl111_drm_dev_private *priv = drm->dev_private;
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writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + CLCD_PL111_IENB);
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return 0;
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}
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void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc)
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{
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struct pl111_drm_dev_private *priv = drm->dev_private;
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writel(0, priv->regs + CLCD_PL111_IENB);
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}
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static int pl111_display_prepare_fb(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *plane_state)
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{
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return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
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}
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const struct drm_simple_display_pipe_funcs pl111_display_funcs = {
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.check = pl111_display_check,
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.enable = pl111_display_enable,
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.disable = pl111_display_disable,
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.update = pl111_display_update,
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.prepare_fb = pl111_display_prepare_fb,
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};
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int pl111_display_init(struct drm_device *drm)
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{
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struct pl111_drm_dev_private *priv = drm->dev_private;
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struct device *dev = drm->dev;
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struct device_node *endpoint;
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u32 tft_r0b0g0[3];
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int ret;
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static const u32 formats[] = {
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_BGR565,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_XBGR1555,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_XRGB1555,
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DRM_FORMAT_ABGR4444,
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DRM_FORMAT_XBGR4444,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_XRGB4444,
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};
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endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
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if (!endpoint)
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return -ENODEV;
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if (of_property_read_u32_array(endpoint,
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"arm,pl11x,tft-r0g0b0-pads",
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tft_r0b0g0,
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ARRAY_SIZE(tft_r0b0g0)) != 0) {
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dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n");
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of_node_put(endpoint);
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return -ENOENT;
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}
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of_node_put(endpoint);
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if (tft_r0b0g0[0] != 0 ||
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tft_r0b0g0[1] != 8 ||
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tft_r0b0g0[2] != 16) {
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dev_err(dev, "arm,pl11x,tft-r0g0b0-pads != [0,8,16] not yet supported\n");
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return -EINVAL;
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}
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ret = drm_simple_display_pipe_init(drm, &priv->pipe,
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&pl111_display_funcs,
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formats, ARRAY_SIZE(formats),
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&priv->connector.connector);
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if (ret)
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return ret;
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return 0;
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}
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