![Linus Walleij](/assets/img/avatar_default.png)
This is a GPIO driver, include only <linux/gpio/driver.h>. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
550 lines
14 KiB
C
550 lines
14 KiB
C
/*
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* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#define PCH_EDGE_FALLING 0
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#define PCH_EDGE_RISING BIT(0)
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#define PCH_LEVEL_L BIT(1)
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#define PCH_LEVEL_H (BIT(0) | BIT(1))
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#define PCH_EDGE_BOTH BIT(2)
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#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
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#define PCH_IRQ_BASE 24
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struct pch_regs {
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u32 ien;
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u32 istatus;
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u32 idisp;
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u32 iclr;
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u32 imask;
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u32 imaskclr;
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u32 po;
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u32 pi;
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u32 pm;
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u32 im0;
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u32 im1;
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u32 reserved[3];
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u32 gpio_use_sel;
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u32 reset;
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};
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enum pch_type_t {
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INTEL_EG20T_PCH,
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OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
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OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
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};
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/* Specifies number of GPIO PINS */
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static int gpio_pins[] = {
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[INTEL_EG20T_PCH] = 12,
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[OKISEMI_ML7223m_IOH] = 8,
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[OKISEMI_ML7223n_IOH] = 8,
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};
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/**
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* struct pch_gpio_reg_data - The register store data.
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* @ien_reg: To store contents of IEN register.
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* @imask_reg: To store contents of IMASK register.
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* @po_reg: To store contents of PO register.
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* @pm_reg: To store contents of PM register.
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* @im0_reg: To store contents of IM0 register.
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* @im1_reg: To store contents of IM1 register.
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* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
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* (Only ML7223 Bus-n)
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*/
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struct pch_gpio_reg_data {
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u32 ien_reg;
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u32 imask_reg;
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u32 po_reg;
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u32 pm_reg;
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u32 im0_reg;
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u32 im1_reg;
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u32 gpio_use_sel_reg;
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};
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/**
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* struct pch_gpio - GPIO private data structure.
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* @base: PCI base address of Memory mapped I/O register.
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* @reg: Memory mapped PCH GPIO register list.
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* @dev: Pointer to device structure.
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* @gpio: Data for GPIO infrastructure.
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* @pch_gpio_reg: Memory mapped Register data is saved here
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* when suspend.
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* @lock: Used for register access protection
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* @irq_base: Save base of IRQ number for interrupt
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* @ioh: IOH ID
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* @spinlock: Used for register access protection
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*/
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struct pch_gpio {
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void __iomem *base;
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struct pch_regs __iomem *reg;
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struct device *dev;
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struct gpio_chip gpio;
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struct pch_gpio_reg_data pch_gpio_reg;
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int irq_base;
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enum pch_type_t ioh;
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spinlock_t spinlock;
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};
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static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
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{
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u32 reg_val;
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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unsigned long flags;
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spin_lock_irqsave(&chip->spinlock, flags);
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reg_val = ioread32(&chip->reg->po);
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if (val)
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reg_val |= (1 << nr);
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else
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reg_val &= ~(1 << nr);
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iowrite32(reg_val, &chip->reg->po);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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}
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static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
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{
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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return (ioread32(&chip->reg->pi) >> nr) & 1;
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}
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static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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int val)
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{
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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u32 pm;
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u32 reg_val;
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unsigned long flags;
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spin_lock_irqsave(&chip->spinlock, flags);
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reg_val = ioread32(&chip->reg->po);
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if (val)
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reg_val |= (1 << nr);
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else
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reg_val &= ~(1 << nr);
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iowrite32(reg_val, &chip->reg->po);
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm |= (1 << nr);
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iowrite32(pm, &chip->reg->pm);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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{
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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u32 pm;
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unsigned long flags;
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spin_lock_irqsave(&chip->spinlock, flags);
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm &= ~(1 << nr);
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iowrite32(pm, &chip->reg->pm);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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#ifdef CONFIG_PM
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/*
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* Save register configuration and disable interrupts.
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*/
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static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
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{
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chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
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chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
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chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
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chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
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chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
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if (chip->ioh == INTEL_EG20T_PCH)
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chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
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if (chip->ioh == OKISEMI_ML7223n_IOH)
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chip->pch_gpio_reg.gpio_use_sel_reg =\
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ioread32(&chip->reg->gpio_use_sel);
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}
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/*
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* This function restores the register configuration of the GPIO device.
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*/
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static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
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{
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iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
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iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
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/* to store contents of PO register */
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iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
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/* to store contents of PM register */
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iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
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iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
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if (chip->ioh == INTEL_EG20T_PCH)
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iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
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if (chip->ioh == OKISEMI_ML7223n_IOH)
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iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
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&chip->reg->gpio_use_sel);
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}
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#endif
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static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
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{
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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return chip->irq_base + offset;
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}
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static void pch_gpio_setup(struct pch_gpio *chip)
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{
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struct gpio_chip *gpio = &chip->gpio;
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gpio->label = dev_name(chip->dev);
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gpio->parent = chip->dev;
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gpio->owner = THIS_MODULE;
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gpio->direction_input = pch_gpio_direction_input;
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gpio->get = pch_gpio_get;
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gpio->direction_output = pch_gpio_direction_output;
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gpio->set = pch_gpio_set;
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gpio->dbg_show = NULL;
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gpio->base = -1;
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gpio->ngpio = gpio_pins[chip->ioh];
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gpio->can_sleep = false;
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gpio->to_irq = pch_gpio_to_irq;
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}
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static int pch_irq_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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u32 im, im_pos, val;
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u32 __iomem *im_reg;
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unsigned long flags;
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int ch, irq = d->irq;
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ch = irq - chip->irq_base;
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if (irq <= chip->irq_base + 7) {
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im_reg = &chip->reg->im0;
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im_pos = ch;
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} else {
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im_reg = &chip->reg->im1;
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im_pos = ch - 8;
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}
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dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
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__func__, irq, type, ch, im_pos);
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spin_lock_irqsave(&chip->spinlock, flags);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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val = PCH_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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val = PCH_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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val = PCH_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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val = PCH_LEVEL_H;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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val = PCH_LEVEL_L;
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break;
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default:
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goto unlock;
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}
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/* Set interrupt mode */
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im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
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iowrite32(im | (val << (im_pos * 4)), im_reg);
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/* And the handler */
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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irq_set_handler_locked(d, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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irq_set_handler_locked(d, handle_edge_irq);
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unlock:
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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static void pch_irq_unmask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
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}
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static void pch_irq_mask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
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}
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static void pch_irq_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
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}
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static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
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{
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struct pch_gpio *chip = dev_id;
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u32 reg_val = ioread32(&chip->reg->istatus);
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int i, ret = IRQ_NONE;
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for (i = 0; i < gpio_pins[chip->ioh]; i++) {
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if (reg_val & BIT(i)) {
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dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
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__func__, i, irq, reg_val);
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generic_handle_irq(chip->irq_base + i);
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ret = IRQ_HANDLED;
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}
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}
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return ret;
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}
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static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
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unsigned int irq_start,
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unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int rv;
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gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
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chip->base, handle_simple_irq);
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if (!gc)
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return -ENOMEM;
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gc->private = chip;
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ct = gc->chip_types;
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ct->chip.irq_ack = pch_irq_ack;
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ct->chip.irq_mask = pch_irq_mask;
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ct->chip.irq_unmask = pch_irq_unmask;
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ct->chip.irq_set_type = pch_irq_type;
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rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
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IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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return rv;
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}
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static int pch_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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s32 ret;
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struct pch_gpio *chip;
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int irq_base;
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u32 msk;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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chip->dev = &pdev->dev;
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
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goto err_pci_enable;
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}
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ret = pci_request_regions(pdev, KBUILD_MODNAME);
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if (ret) {
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dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
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goto err_request_regions;
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}
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chip->base = pci_iomap(pdev, 1, 0);
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if (!chip->base) {
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dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
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ret = -ENOMEM;
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goto err_iomap;
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}
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if (pdev->device == 0x8803)
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chip->ioh = INTEL_EG20T_PCH;
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else if (pdev->device == 0x8014)
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chip->ioh = OKISEMI_ML7223m_IOH;
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else if (pdev->device == 0x8043)
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chip->ioh = OKISEMI_ML7223n_IOH;
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chip->reg = chip->base;
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pci_set_drvdata(pdev, chip);
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spin_lock_init(&chip->spinlock);
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pch_gpio_setup(chip);
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#ifdef CONFIG_OF_GPIO
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chip->gpio.of_node = pdev->dev.of_node;
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#endif
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ret = gpiochip_add_data(&chip->gpio, chip);
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if (ret) {
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dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
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goto err_gpiochip_add;
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}
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irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
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gpio_pins[chip->ioh], NUMA_NO_NODE);
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if (irq_base < 0) {
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dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
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chip->irq_base = -1;
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goto end;
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}
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chip->irq_base = irq_base;
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/* Mask all interrupts, but enable them */
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msk = (1 << gpio_pins[chip->ioh]) - 1;
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iowrite32(msk, &chip->reg->imask);
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iowrite32(msk, &chip->reg->ien);
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ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
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IRQF_SHARED, KBUILD_MODNAME, chip);
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if (ret != 0) {
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dev_err(&pdev->dev,
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"%s request_irq failed\n", __func__);
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goto err_request_irq;
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}
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ret = pch_gpio_alloc_generic_chip(chip, irq_base,
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gpio_pins[chip->ioh]);
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if (ret)
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goto err_request_irq;
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end:
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return 0;
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err_request_irq:
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gpiochip_remove(&chip->gpio);
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err_gpiochip_add:
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pci_iounmap(pdev, chip->base);
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err_iomap:
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pci_release_regions(pdev);
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err_request_regions:
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pci_disable_device(pdev);
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err_pci_enable:
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kfree(chip);
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dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
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return ret;
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}
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static void pch_gpio_remove(struct pci_dev *pdev)
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{
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struct pch_gpio *chip = pci_get_drvdata(pdev);
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gpiochip_remove(&chip->gpio);
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pci_iounmap(pdev, chip->base);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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kfree(chip);
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}
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#ifdef CONFIG_PM
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static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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s32 ret;
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struct pch_gpio *chip = pci_get_drvdata(pdev);
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unsigned long flags;
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spin_lock_irqsave(&chip->spinlock, flags);
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pch_gpio_save_reg_conf(chip);
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spin_unlock_irqrestore(&chip->spinlock, flags);
|
|
|
|
ret = pci_save_state(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
|
|
return ret;
|
|
}
|
|
pci_disable_device(pdev);
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
ret = pci_enable_wake(pdev, PCI_D0, 1);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pch_gpio_resume(struct pci_dev *pdev)
|
|
{
|
|
s32 ret;
|
|
struct pch_gpio *chip = pci_get_drvdata(pdev);
|
|
unsigned long flags;
|
|
|
|
ret = pci_enable_wake(pdev, PCI_D0, 0);
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
ret = pci_enable_device(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
|
|
return ret;
|
|
}
|
|
pci_restore_state(pdev);
|
|
|
|
spin_lock_irqsave(&chip->spinlock, flags);
|
|
iowrite32(0x01, &chip->reg->reset);
|
|
iowrite32(0x00, &chip->reg->reset);
|
|
pch_gpio_restore_reg_conf(chip);
|
|
spin_unlock_irqrestore(&chip->spinlock, flags);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define pch_gpio_suspend NULL
|
|
#define pch_gpio_resume NULL
|
|
#endif
|
|
|
|
#define PCI_VENDOR_ID_ROHM 0x10DB
|
|
static const struct pci_device_id pch_gpio_pcidev_id[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
|
|
{ 0, }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
|
|
|
|
static struct pci_driver pch_gpio_driver = {
|
|
.name = "pch_gpio",
|
|
.id_table = pch_gpio_pcidev_id,
|
|
.probe = pch_gpio_probe,
|
|
.remove = pch_gpio_remove,
|
|
.suspend = pch_gpio_suspend,
|
|
.resume = pch_gpio_resume
|
|
};
|
|
|
|
module_pci_driver(pch_gpio_driver);
|
|
|
|
MODULE_DESCRIPTION("PCH GPIO PCI Driver");
|
|
MODULE_LICENSE("GPL");
|