![Joel Stanley](/assets/img/avatar_default.png)
ASPEED BMC SoCs have a reset controller in the LPC IP that can be controlled using this driver to release the UARTs from reset. No special configuration is required, so only the compatible string is added. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
189 lines
5.2 KiB
C
189 lines
5.2 KiB
C
/*
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* Simple Reset Controller Driver
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*
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* Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
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*
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* Based on Allwinner SoCs Reset Controller driver
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*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include "reset-simple.h"
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static inline struct reset_simple_data *
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to_reset_simple_data(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct reset_simple_data, rcdev);
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}
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static int reset_simple_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct reset_simple_data *data = to_reset_simple_data(rcdev);
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + (bank * reg_width));
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if (assert ^ data->active_low)
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reg |= BIT(offset);
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else
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reg &= ~BIT(offset);
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writel(reg, data->membase + (bank * reg_width));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int reset_simple_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return reset_simple_update(rcdev, id, true);
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}
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static int reset_simple_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return reset_simple_update(rcdev, id, false);
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}
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static int reset_simple_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct reset_simple_data *data = to_reset_simple_data(rcdev);
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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u32 reg;
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reg = readl(data->membase + (bank * reg_width));
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return !(reg & BIT(offset)) ^ !data->status_active_low;
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}
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const struct reset_control_ops reset_simple_ops = {
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.assert = reset_simple_assert,
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.deassert = reset_simple_deassert,
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.status = reset_simple_status,
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};
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/**
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* struct reset_simple_devdata - simple reset controller properties
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* @reg_offset: offset between base address and first reset register.
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* @nr_resets: number of resets. If not set, default to resource size in bits.
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* @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
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* are set to assert the reset.
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* @status_active_low: if true, bits read back as cleared while the reset is
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* asserted. Otherwise, bits read back as set while the
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* reset is asserted.
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*/
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struct reset_simple_devdata {
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u32 reg_offset;
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u32 nr_resets;
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bool active_low;
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bool status_active_low;
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};
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#define SOCFPGA_NR_BANKS 8
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static const struct reset_simple_devdata reset_simple_socfpga = {
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.reg_offset = 0x10,
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.nr_resets = SOCFPGA_NR_BANKS * 32,
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.status_active_low = true,
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};
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static const struct reset_simple_devdata reset_simple_active_low = {
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.active_low = true,
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.status_active_low = true,
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};
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static const struct of_device_id reset_simple_dt_ids[] = {
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{ .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
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{ .compatible = "st,stm32-rcc", },
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{ .compatible = "allwinner,sun6i-a31-clock-reset",
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.data = &reset_simple_active_low },
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{ .compatible = "zte,zx296718-reset",
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.data = &reset_simple_active_low },
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{ .compatible = "aspeed,ast2400-lpc-reset" },
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{ .compatible = "aspeed,ast2500-lpc-reset" },
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{ /* sentinel */ },
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};
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static int reset_simple_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct reset_simple_devdata *devdata;
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struct reset_simple_data *data;
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void __iomem *membase;
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struct resource *res;
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u32 reg_offset = 0;
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devdata = of_device_get_match_data(dev);
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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membase = devm_ioremap_resource(dev, res);
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if (IS_ERR(membase))
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return PTR_ERR(membase);
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spin_lock_init(&data->lock);
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data->membase = membase;
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
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data->rcdev.ops = &reset_simple_ops;
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data->rcdev.of_node = dev->of_node;
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if (devdata) {
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reg_offset = devdata->reg_offset;
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if (devdata->nr_resets)
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data->rcdev.nr_resets = devdata->nr_resets;
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data->active_low = devdata->active_low;
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data->status_active_low = devdata->status_active_low;
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}
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if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
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of_property_read_u32(dev->of_node, "altr,modrst-offset",
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®_offset)) {
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dev_warn(dev,
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"missing altr,modrst-offset property, assuming 0x%x!\n",
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reg_offset);
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}
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data->membase += reg_offset;
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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static struct platform_driver reset_simple_driver = {
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.probe = reset_simple_probe,
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.driver = {
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.name = "simple-reset",
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.of_match_table = reset_simple_dt_ids,
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},
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};
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builtin_platform_driver(reset_simple_driver);
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