![Kevin Hilman](/assets/img/avatar_default.png)
This branch includes a number of enhancements to core SoC support for Tegra devices. The major new features are: * Adds a new CPU-power-gated cpuidle state for Tegra114. * Adds initial system suspend support for Tegra114, initially supporting just CPU-power-gating during suspend. * Adds "LP1" suspend mode support for all of Tegra20/30/114. This mode both gates CPU power, and places the DRAM into self-refresh mode. * A new DT-driven PCIe driver to Tegra20/30. The driver is also moved from arch/arm/mach-tegra/ to drivers/pci/host/. The PCIe driver work depends on the following tag from Thomas Petazzoni: git://git.infradead.org/linux-mvebu.git mis-3.12.2 ... which is merged into the middle of this pull request. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSDlwwAAoJEMzrak5tbycxR68QAJZ/Izc9Izj0JH8hmCEvMNfi ub1DQfWAy3oXk0ttkk+BMvuyD8JTvBr8LSK8GqjZs//rFGlW81A4NHTvCwoKZjKe hgrRgI2B1wj3Um1sp8le9D0klKrTcfmpXrOxH8ALgz0BIpMge8AGZHkV0SrfQa1z bKiISFVAw12WJCVrQ2nbzpZGU51lbyJ/+RghttM1a8LuS2P03CZgt2kqiytk3UVK uiGEy3sCkjXLFO3EsUvM6ha623S6BumCAYjNfgDowTVKaoEe1r2TD4bFeU6lGcXJ mlVTv0Kywazf4Q2gKzkbDz8UQMArW4hok2iILHzz+sf/Rn0hie5XVqhFlbBlcae8 vyWsHmqvmE9BJAK2G2RLs9cJCTzEpEyAjUWfE3sIIa3ztSguT5+PHndDLR/d76aS j8L3FYReICZ1NuNw1JSQPFs9g2EWJbNRiy+8o9O2elsJMpLDBj/FcV6TVpudbBTI z7hvN+XSVYUaCVD4e8ma9YoC3VGseiAZvd+Y8hPd2MFBECVPNpy2bOacieU6Bgxh zjSBXZ/URxN3rTkv9+F3BLWAOfVmJYN0rKV9YfM/rqpWjc9iQx30m1fRZDnXWhvd ps8eFIYsKqc6v9AAugl/RexFy4Laav9eREjb0k2LA8ClLhK/qLLuiisVmKWS/grh lX9tzPEG2nZcjxSYaEjz =ve9i -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From: Stephen Warren: ARM: tegra: core SoC enhancements for 3.12 This branch includes a number of enhancements to core SoC support for Tegra devices. The major new features are: * Adds a new CPU-power-gated cpuidle state for Tegra114. * Adds initial system suspend support for Tegra114, initially supporting just CPU-power-gating during suspend. * Adds "LP1" suspend mode support for all of Tegra20/30/114. This mode both gates CPU power, and places the DRAM into self-refresh mode. * A new DT-driven PCIe driver to Tegra20/30. The driver is also moved from arch/arm/mach-tegra/ to drivers/pci/host/. The PCIe driver work depends on the following tag from Thomas Petazzoni: git://git.infradead.org/linux-mvebu.git mis-3.12.2 ... which is merged into the middle of this pull request. * tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (33 commits) ARM: tegra: disable LP2 cpuidle state if PCIe is enabled MAINTAINERS: Add myself as Tegra PCIe maintainer PCI: tegra: set up PADS_REFCLK_CFG1 PCI: tegra: Add Tegra 30 PCIe support PCI: tegra: Move PCIe driver to drivers/pci/host PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platforms ARM: tegra: add LP1 suspend support for Tegra114 ARM: tegra: add LP1 suspend support for Tegra20 ARM: tegra: add LP1 suspend support for Tegra30 ARM: tegra: add common LP1 suspend support clk: tegra114: add LP1 suspend/resume support ARM: tegra: config the polarity of the request of sys clock ARM: tegra: add common resume handling code for LP1 resuming ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci of: pci: add registry of MSI chips PCI: Introduce new MSI chip infrastructure PCI: remove ARCH_SUPPORTS_MSI kconfig option PCI: use weak functions for MSI arch-specific functions ARM: tegra: unify Tegra's Kconfig a bit more ARM: tegra: remove the limitation that Tegra114 can't support suspend ... Signed-off-by: Kevin Hilman <khilman@linaro.org>
377 lines
7.9 KiB
C
377 lines
7.9 KiB
C
/*
|
|
* CPU complex suspend & resume functions for Tegra SoCs
|
|
*
|
|
* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/spinlock.h>
|
|
#include <linux/io.h>
|
|
#include <linux/cpumask.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/cpu_pm.h>
|
|
#include <linux/suspend.h>
|
|
#include <linux/err.h>
|
|
#include <linux/clk/tegra.h>
|
|
|
|
#include <asm/smp_plat.h>
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/suspend.h>
|
|
#include <asm/idmap.h>
|
|
#include <asm/proc-fns.h>
|
|
#include <asm/tlbflush.h>
|
|
|
|
#include "iomap.h"
|
|
#include "reset.h"
|
|
#include "flowctrl.h"
|
|
#include "fuse.h"
|
|
#include "pm.h"
|
|
#include "pmc.h"
|
|
#include "sleep.h"
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static DEFINE_SPINLOCK(tegra_lp2_lock);
|
|
static u32 iram_save_size;
|
|
static void *iram_save_addr;
|
|
struct tegra_lp1_iram tegra_lp1_iram;
|
|
void (*tegra_tear_down_cpu)(void);
|
|
void (*tegra_sleep_core_finish)(unsigned long v2p);
|
|
static int (*tegra_sleep_func)(unsigned long v2p);
|
|
|
|
static void tegra_tear_down_cpu_init(void)
|
|
{
|
|
switch (tegra_chip_id) {
|
|
case TEGRA20:
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
|
|
tegra_tear_down_cpu = tegra20_tear_down_cpu;
|
|
break;
|
|
case TEGRA30:
|
|
case TEGRA114:
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
|
|
tegra_tear_down_cpu = tegra30_tear_down_cpu;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* restore_cpu_complex
|
|
*
|
|
* restores cpu clock setting, clears flow controller
|
|
*
|
|
* Always called on CPU 0.
|
|
*/
|
|
static void restore_cpu_complex(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
BUG_ON(cpu != 0);
|
|
|
|
#ifdef CONFIG_SMP
|
|
cpu = cpu_logical_map(cpu);
|
|
#endif
|
|
|
|
/* Restore the CPU clock settings */
|
|
tegra_cpu_clock_resume();
|
|
|
|
flowctrl_cpu_suspend_exit(cpu);
|
|
}
|
|
|
|
/*
|
|
* suspend_cpu_complex
|
|
*
|
|
* saves pll state for use by restart_plls, prepares flow controller for
|
|
* transition to suspend state
|
|
*
|
|
* Must always be called on cpu 0.
|
|
*/
|
|
static void suspend_cpu_complex(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
BUG_ON(cpu != 0);
|
|
|
|
#ifdef CONFIG_SMP
|
|
cpu = cpu_logical_map(cpu);
|
|
#endif
|
|
|
|
/* Save the CPU clock settings */
|
|
tegra_cpu_clock_suspend();
|
|
|
|
flowctrl_cpu_suspend_enter(cpu);
|
|
}
|
|
|
|
void tegra_clear_cpu_in_lp2(void)
|
|
{
|
|
int phy_cpu_id = cpu_logical_map(smp_processor_id());
|
|
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
|
|
|
|
spin_lock(&tegra_lp2_lock);
|
|
|
|
BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
|
|
*cpu_in_lp2 &= ~BIT(phy_cpu_id);
|
|
|
|
spin_unlock(&tegra_lp2_lock);
|
|
}
|
|
|
|
bool tegra_set_cpu_in_lp2(void)
|
|
{
|
|
int phy_cpu_id = cpu_logical_map(smp_processor_id());
|
|
bool last_cpu = false;
|
|
cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
|
|
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
|
|
|
|
spin_lock(&tegra_lp2_lock);
|
|
|
|
BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
|
|
*cpu_in_lp2 |= BIT(phy_cpu_id);
|
|
|
|
if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
|
|
last_cpu = true;
|
|
else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
|
|
tegra20_cpu_set_resettable_soon();
|
|
|
|
spin_unlock(&tegra_lp2_lock);
|
|
return last_cpu;
|
|
}
|
|
|
|
int tegra_cpu_do_idle(void)
|
|
{
|
|
return cpu_do_idle();
|
|
}
|
|
|
|
static int tegra_sleep_cpu(unsigned long v2p)
|
|
{
|
|
setup_mm_for_reboot();
|
|
tegra_sleep_cpu_finish(v2p);
|
|
|
|
/* should never here */
|
|
BUG();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void tegra_idle_lp2_last(void)
|
|
{
|
|
tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
|
|
|
|
cpu_cluster_pm_enter();
|
|
suspend_cpu_complex();
|
|
|
|
cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
|
|
|
|
restore_cpu_complex();
|
|
cpu_cluster_pm_exit();
|
|
}
|
|
|
|
enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
|
|
enum tegra_suspend_mode mode)
|
|
{
|
|
/*
|
|
* The Tegra devices support suspending to LP1 or lower currently.
|
|
*/
|
|
if (mode > TEGRA_SUSPEND_LP1)
|
|
return TEGRA_SUSPEND_LP1;
|
|
|
|
return mode;
|
|
}
|
|
|
|
static int tegra_sleep_core(unsigned long v2p)
|
|
{
|
|
setup_mm_for_reboot();
|
|
tegra_sleep_core_finish(v2p);
|
|
|
|
/* should never here */
|
|
BUG();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* tegra_lp1_iram_hook
|
|
*
|
|
* Hooking the address of LP1 reset vector and SDRAM self-refresh code in
|
|
* SDRAM. These codes not be copied to IRAM in this fuction. We need to
|
|
* copy these code to IRAM before LP0/LP1 suspend and restore the content
|
|
* of IRAM after resume.
|
|
*/
|
|
static bool tegra_lp1_iram_hook(void)
|
|
{
|
|
switch (tegra_chip_id) {
|
|
case TEGRA20:
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
|
|
tegra20_lp1_iram_hook();
|
|
break;
|
|
case TEGRA30:
|
|
case TEGRA114:
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
|
|
tegra30_lp1_iram_hook();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
|
|
return false;
|
|
|
|
iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
|
|
iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
|
|
if (!iram_save_addr)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool tegra_sleep_core_init(void)
|
|
{
|
|
switch (tegra_chip_id) {
|
|
case TEGRA20:
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
|
|
tegra20_sleep_core_init();
|
|
break;
|
|
case TEGRA30:
|
|
case TEGRA114:
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
|
|
tegra30_sleep_core_init();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!tegra_sleep_core_finish)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static void tegra_suspend_enter_lp1(void)
|
|
{
|
|
tegra_pmc_suspend();
|
|
|
|
/* copy the reset vector & SDRAM shutdown code into IRAM */
|
|
memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
|
|
iram_save_size);
|
|
memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
|
|
iram_save_size);
|
|
|
|
*((u32 *)tegra_cpu_lp1_mask) = 1;
|
|
}
|
|
|
|
static void tegra_suspend_exit_lp1(void)
|
|
{
|
|
tegra_pmc_resume();
|
|
|
|
/* restore IRAM */
|
|
memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
|
|
iram_save_size);
|
|
|
|
*(u32 *)tegra_cpu_lp1_mask = 0;
|
|
}
|
|
|
|
static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
|
|
[TEGRA_SUSPEND_NONE] = "none",
|
|
[TEGRA_SUSPEND_LP2] = "LP2",
|
|
[TEGRA_SUSPEND_LP1] = "LP1",
|
|
[TEGRA_SUSPEND_LP0] = "LP0",
|
|
};
|
|
|
|
static int tegra_suspend_enter(suspend_state_t state)
|
|
{
|
|
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
|
|
|
|
if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
|
|
mode >= TEGRA_MAX_SUSPEND_MODE))
|
|
return -EINVAL;
|
|
|
|
pr_info("Entering suspend state %s\n", lp_state[mode]);
|
|
|
|
tegra_pmc_pm_set(mode);
|
|
|
|
local_fiq_disable();
|
|
|
|
suspend_cpu_complex();
|
|
switch (mode) {
|
|
case TEGRA_SUSPEND_LP1:
|
|
tegra_suspend_enter_lp1();
|
|
break;
|
|
case TEGRA_SUSPEND_LP2:
|
|
tegra_set_cpu_in_lp2();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
|
|
|
|
switch (mode) {
|
|
case TEGRA_SUSPEND_LP1:
|
|
tegra_suspend_exit_lp1();
|
|
break;
|
|
case TEGRA_SUSPEND_LP2:
|
|
tegra_clear_cpu_in_lp2();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
restore_cpu_complex();
|
|
|
|
local_fiq_enable();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_suspend_ops tegra_suspend_ops = {
|
|
.valid = suspend_valid_only_mem,
|
|
.enter = tegra_suspend_enter,
|
|
};
|
|
|
|
void __init tegra_init_suspend(void)
|
|
{
|
|
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
|
|
|
|
if (mode == TEGRA_SUSPEND_NONE)
|
|
return;
|
|
|
|
tegra_tear_down_cpu_init();
|
|
tegra_pmc_suspend_init();
|
|
|
|
if (mode >= TEGRA_SUSPEND_LP1) {
|
|
if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
|
|
pr_err("%s: unable to allocate memory for SDRAM"
|
|
"self-refresh -- LP0/LP1 unavailable\n",
|
|
__func__);
|
|
tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
|
|
mode = TEGRA_SUSPEND_LP2;
|
|
}
|
|
}
|
|
|
|
/* set up sleep function for cpu_suspend */
|
|
switch (mode) {
|
|
case TEGRA_SUSPEND_LP1:
|
|
tegra_sleep_func = tegra_sleep_core;
|
|
break;
|
|
case TEGRA_SUSPEND_LP2:
|
|
tegra_sleep_func = tegra_sleep_cpu;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
suspend_set_ops(&tegra_suspend_ops);
|
|
}
|
|
#endif
|