c06e64407e
The firmware sets BIT(13) in clkflag to mark a divider as fractional divider. The clock driver copies the clkflag straight to the flags of the common clock framework. In the common clk framework flags, BIT(13) is defined as CLK_DUTY_CYCLE_PARENT. Add a new field to the zynqmp_clk_divider to specify if a divider is a fractional devider. Set this field based on the clkflag when registering a divider. At the same time, unset BIT(13) from clkflag when copying the flags to the common clk framework flags. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| clk-gate-zynqmp.c | ||
| clk-mux-zynqmp.c | ||
| clk-zynqmp.h | ||
| clkc.c | ||
| divider.c | ||
| Kconfig | ||
| Makefile | ||
| pll.c | ||