![Abhilash Kesavan](/assets/img/avatar_default.png)
We have an soc check to ensure that the scu and certain A9 specific registers are not accessed on Exynos5250 (which is A15 based). Rather than adding another soc specific check for 5420 let us test for the Cortex A9 primary part number. This resolves the below crash seen on exynos5420 during core switching after the CPUIdle consolidation series was merged. [ 155.975589] [<c0013174>] (scu_enable) from [<c001b0dc>] (exynos_cpu_pm_notifier+0x80/0xc4) [ 155.983833] [<c001b0dc>] (exynos_cpu_pm_notifier) from [<c003c1b0>] (notifier_call_chain+0x44/0x84) [ 155.992851] [<c003c1b0>] (notifier_call_chain) from [<c007a49c>] (cpu_pm_notify+0x20/0x3c) [ 156.001089] [<c007a49c>] (cpu_pm_notify) from [<c007a564>] (cpu_pm_exit+0x20/0x38) [ 156.008635] [<c007a564>] (cpu_pm_exit) from [<c0019e98>] (bL_switcher_thread+0x298/0x40c) [ 156.016788] [<c0019e98>] (bL_switcher_thread) from [<c003842c>] (kthread+0xcc/0xe8) [ 156.024426] [<c003842c>] (kthread) from [<c000e438>] (ret_from_fork+0x14/0x3c) [ 156.031621] Code: ea017fec c0530a00 c052e3f8 c0012dcc (e5903000 Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
484 lines
11 KiB
C
484 lines
11 KiB
C
/*
|
|
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* EXYNOS - Power Management support
|
|
*
|
|
* Based on arch/arm/mach-s3c2410/pm.c
|
|
* Copyright (c) 2006 Simtec Electronics
|
|
* Ben Dooks <ben@simtec.co.uk>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/suspend.h>
|
|
#include <linux/syscore_ops.h>
|
|
#include <linux/cpu_pm.h>
|
|
#include <linux/io.h>
|
|
#include <linux/irqchip/arm-gic.h>
|
|
#include <linux/err.h>
|
|
#include <linux/clk.h>
|
|
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/hardware/cache-l2x0.h>
|
|
#include <asm/smp_scu.h>
|
|
#include <asm/suspend.h>
|
|
|
|
#include <plat/pm-common.h>
|
|
#include <plat/pll.h>
|
|
#include <plat/regs-srom.h>
|
|
|
|
#include <mach/map.h>
|
|
|
|
#include "common.h"
|
|
#include "regs-pmu.h"
|
|
|
|
/**
|
|
* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
|
|
* @hwirq: Hardware IRQ signal of the GIC
|
|
* @mask: Mask in PMU wake-up mask register
|
|
*/
|
|
struct exynos_wkup_irq {
|
|
unsigned int hwirq;
|
|
u32 mask;
|
|
};
|
|
|
|
static struct sleep_save exynos5_sys_save[] = {
|
|
SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
|
|
};
|
|
|
|
static struct sleep_save exynos_core_save[] = {
|
|
/* SROM side */
|
|
SAVE_ITEM(S5P_SROM_BW),
|
|
SAVE_ITEM(S5P_SROM_BC0),
|
|
SAVE_ITEM(S5P_SROM_BC1),
|
|
SAVE_ITEM(S5P_SROM_BC2),
|
|
SAVE_ITEM(S5P_SROM_BC3),
|
|
};
|
|
|
|
/*
|
|
* GIC wake-up support
|
|
*/
|
|
|
|
static u32 exynos_irqwake_intmask = 0xffffffff;
|
|
|
|
static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
|
|
{ 76, BIT(1) }, /* RTC alarm */
|
|
{ 77, BIT(2) }, /* RTC tick */
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
|
|
{ 75, BIT(1) }, /* RTC alarm */
|
|
{ 76, BIT(2) }, /* RTC tick */
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
|
|
{
|
|
const struct exynos_wkup_irq *wkup_irq;
|
|
|
|
if (soc_is_exynos5250())
|
|
wkup_irq = exynos5250_wkup_irq;
|
|
else
|
|
wkup_irq = exynos4_wkup_irq;
|
|
|
|
while (wkup_irq->mask) {
|
|
if (wkup_irq->hwirq == data->hwirq) {
|
|
if (!state)
|
|
exynos_irqwake_intmask |= wkup_irq->mask;
|
|
else
|
|
exynos_irqwake_intmask &= ~wkup_irq->mask;
|
|
return 0;
|
|
}
|
|
++wkup_irq;
|
|
}
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
/**
|
|
* exynos_core_power_down : power down the specified cpu
|
|
* @cpu : the cpu to power down
|
|
*
|
|
* Power down the specified cpu. The sequence must be finished by a
|
|
* call to cpu_do_idle()
|
|
*
|
|
*/
|
|
void exynos_cpu_power_down(int cpu)
|
|
{
|
|
__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
|
|
}
|
|
|
|
/**
|
|
* exynos_cpu_power_up : power up the specified cpu
|
|
* @cpu : the cpu to power up
|
|
*
|
|
* Power up the specified cpu
|
|
*/
|
|
void exynos_cpu_power_up(int cpu)
|
|
{
|
|
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
|
|
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
|
|
}
|
|
|
|
/**
|
|
* exynos_cpu_power_state : returns the power state of the cpu
|
|
* @cpu : the cpu to retrieve the power state from
|
|
*
|
|
*/
|
|
int exynos_cpu_power_state(int cpu)
|
|
{
|
|
return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
|
|
S5P_CORE_LOCAL_PWR_EN);
|
|
}
|
|
|
|
/**
|
|
* exynos_cluster_power_down : power down the specified cluster
|
|
* @cluster : the cluster to power down
|
|
*/
|
|
void exynos_cluster_power_down(int cluster)
|
|
{
|
|
__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
|
|
}
|
|
|
|
/**
|
|
* exynos_cluster_power_up : power up the specified cluster
|
|
* @cluster : the cluster to power up
|
|
*/
|
|
void exynos_cluster_power_up(int cluster)
|
|
{
|
|
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
|
|
EXYNOS_COMMON_CONFIGURATION(cluster));
|
|
}
|
|
|
|
/**
|
|
* exynos_cluster_power_state : returns the power state of the cluster
|
|
* @cluster : the cluster to retrieve the power state from
|
|
*
|
|
*/
|
|
int exynos_cluster_power_state(int cluster)
|
|
{
|
|
return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
|
|
S5P_CORE_LOCAL_PWR_EN);
|
|
}
|
|
|
|
#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
|
|
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
|
|
(sysram_base_addr + 0x24) : S5P_INFORM0))
|
|
#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
|
|
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
|
|
(sysram_base_addr + 0x20) : S5P_INFORM1))
|
|
|
|
#define S5P_CHECK_AFTR 0xFCBA0D10
|
|
#define S5P_CHECK_SLEEP 0x00000BAD
|
|
|
|
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
|
|
static void exynos_set_wakeupmask(long mask)
|
|
{
|
|
__raw_writel(mask, S5P_WAKEUP_MASK);
|
|
}
|
|
|
|
static void exynos_cpu_set_boot_vector(long flags)
|
|
{
|
|
__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
|
|
__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
|
|
}
|
|
|
|
void exynos_enter_aftr(void)
|
|
{
|
|
exynos_set_wakeupmask(0x0000ff3e);
|
|
exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
|
|
/* Set value of power down register for aftr mode */
|
|
exynos_sys_powerdown_conf(SYS_AFTR);
|
|
}
|
|
|
|
/* For Cortex-A9 Diagnostic and Power control register */
|
|
static unsigned int save_arm_register[2];
|
|
|
|
static void exynos_cpu_save_register(void)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
/* Save Power control register */
|
|
asm ("mrc p15, 0, %0, c15, c0, 0"
|
|
: "=r" (tmp) : : "cc");
|
|
|
|
save_arm_register[0] = tmp;
|
|
|
|
/* Save Diagnostic register */
|
|
asm ("mrc p15, 0, %0, c15, c0, 1"
|
|
: "=r" (tmp) : : "cc");
|
|
|
|
save_arm_register[1] = tmp;
|
|
}
|
|
|
|
static void exynos_cpu_restore_register(void)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
/* Restore Power control register */
|
|
tmp = save_arm_register[0];
|
|
|
|
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
|
|
: : "r" (tmp)
|
|
: "cc");
|
|
|
|
/* Restore Diagnostic register */
|
|
tmp = save_arm_register[1];
|
|
|
|
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
|
|
: : "r" (tmp)
|
|
: "cc");
|
|
}
|
|
|
|
static int exynos_cpu_suspend(unsigned long arg)
|
|
{
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
outer_flush_all();
|
|
#endif
|
|
|
|
if (soc_is_exynos5250())
|
|
flush_cache_all();
|
|
|
|
/* issue the standby signal into the pm unit. */
|
|
cpu_do_idle();
|
|
|
|
pr_info("Failed to suspend the system\n");
|
|
return 1; /* Aborting suspend */
|
|
}
|
|
|
|
static void exynos_pm_prepare(void)
|
|
{
|
|
unsigned int tmp;
|
|
|
|
/* Set wake-up mask registers */
|
|
__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
|
|
__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
|
|
|
|
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
|
|
|
if (soc_is_exynos5250()) {
|
|
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
|
|
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
|
|
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
|
|
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
|
|
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
|
|
}
|
|
|
|
/* Set value of power down register for sleep mode */
|
|
|
|
exynos_sys_powerdown_conf(SYS_SLEEP);
|
|
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
|
|
|
|
/* ensure at least INFORM0 has the resume address */
|
|
|
|
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
|
|
}
|
|
|
|
static void exynos_pm_central_suspend(void)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
/* Setting Central Sequence Register for power down mode */
|
|
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
|
|
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
|
|
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
|
}
|
|
|
|
static int exynos_pm_suspend(void)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
exynos_pm_central_suspend();
|
|
|
|
/* Setting SEQ_OPTION register */
|
|
|
|
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
|
|
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
|
|
|
|
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
|
|
exynos_cpu_save_register();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_pm_central_resume(void)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
/*
|
|
* If PMU failed while entering sleep mode, WFI will be
|
|
* ignored by PMU and then exiting cpu_do_idle().
|
|
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
|
|
* in this situation.
|
|
*/
|
|
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
|
|
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
|
|
tmp |= S5P_CENTRAL_LOWPWR_CFG;
|
|
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
|
/* clear the wakeup state register */
|
|
__raw_writel(0x0, S5P_WAKEUP_STAT);
|
|
/* No need to perform below restore code */
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_pm_resume(void)
|
|
{
|
|
if (exynos_pm_central_resume())
|
|
goto early_wakeup;
|
|
|
|
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
|
|
exynos_cpu_restore_register();
|
|
|
|
/* For release retention */
|
|
|
|
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
|
|
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
|
|
|
|
if (soc_is_exynos5250())
|
|
s3c_pm_do_restore(exynos5_sys_save,
|
|
ARRAY_SIZE(exynos5_sys_save));
|
|
|
|
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
|
|
|
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
|
|
scu_enable(S5P_VA_SCU);
|
|
|
|
early_wakeup:
|
|
|
|
/* Clear SLEEP mode set in INFORM1 */
|
|
__raw_writel(0x0, S5P_INFORM1);
|
|
|
|
return;
|
|
}
|
|
|
|
static struct syscore_ops exynos_pm_syscore_ops = {
|
|
.suspend = exynos_pm_suspend,
|
|
.resume = exynos_pm_resume,
|
|
};
|
|
|
|
/*
|
|
* Suspend Ops
|
|
*/
|
|
|
|
static int exynos_suspend_enter(suspend_state_t state)
|
|
{
|
|
int ret;
|
|
|
|
s3c_pm_debug_init();
|
|
|
|
S3C_PMDBG("%s: suspending the system...\n", __func__);
|
|
|
|
S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
|
|
exynos_irqwake_intmask, exynos_get_eint_wake_mask());
|
|
|
|
if (exynos_irqwake_intmask == -1U
|
|
&& exynos_get_eint_wake_mask() == -1U) {
|
|
pr_err("%s: No wake-up sources!\n", __func__);
|
|
pr_err("%s: Aborting sleep\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
s3c_pm_save_uarts();
|
|
exynos_pm_prepare();
|
|
flush_cache_all();
|
|
s3c_pm_check_store();
|
|
|
|
ret = cpu_suspend(0, exynos_cpu_suspend);
|
|
if (ret)
|
|
return ret;
|
|
|
|
s3c_pm_restore_uarts();
|
|
|
|
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
|
|
__raw_readl(S5P_WAKEUP_STAT));
|
|
|
|
s3c_pm_check_restore();
|
|
|
|
S3C_PMDBG("%s: resuming the system...\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_suspend_prepare(void)
|
|
{
|
|
s3c_pm_check_prepare();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void exynos_suspend_finish(void)
|
|
{
|
|
s3c_pm_check_cleanup();
|
|
}
|
|
|
|
static const struct platform_suspend_ops exynos_suspend_ops = {
|
|
.enter = exynos_suspend_enter,
|
|
.prepare = exynos_suspend_prepare,
|
|
.finish = exynos_suspend_finish,
|
|
.valid = suspend_valid_only_mem,
|
|
};
|
|
|
|
static int exynos_cpu_pm_notifier(struct notifier_block *self,
|
|
unsigned long cmd, void *v)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
switch (cmd) {
|
|
case CPU_PM_ENTER:
|
|
if (cpu == 0) {
|
|
exynos_pm_central_suspend();
|
|
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
|
|
exynos_cpu_save_register();
|
|
}
|
|
break;
|
|
|
|
case CPU_PM_EXIT:
|
|
if (cpu == 0) {
|
|
if (read_cpuid_part_number() ==
|
|
ARM_CPU_PART_CORTEX_A9) {
|
|
scu_enable(S5P_VA_SCU);
|
|
exynos_cpu_restore_register();
|
|
}
|
|
exynos_pm_central_resume();
|
|
}
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block exynos_cpu_pm_notifier_block = {
|
|
.notifier_call = exynos_cpu_pm_notifier,
|
|
};
|
|
|
|
void __init exynos_pm_init(void)
|
|
{
|
|
u32 tmp;
|
|
|
|
cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
|
|
|
|
/* Platform-specific GIC callback */
|
|
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
|
|
|
|
/* All wakeup disable */
|
|
tmp = __raw_readl(S5P_WAKEUP_MASK);
|
|
tmp |= ((0xFF << 8) | (0x1F << 1));
|
|
__raw_writel(tmp, S5P_WAKEUP_MASK);
|
|
|
|
register_syscore_ops(&exynos_pm_syscore_ops);
|
|
suspend_set_ops(&exynos_suspend_ops);
|
|
}
|