The interrupter register set includes a register that says whether interrupts
are pending for each event ring (the IP bit). Each MSI-X vector will get its
own interrupter set with separate IP bits. The status register includes an
"Event Interrupt (EINT)" bit that is set when an IP bit is set in any of the
interrupters.
When PCI interrupts are used, the EINT bit exactly mirrors the IP bit in the
single interrupter set, and it is a waste of time to check both registers when
trying to figure out if the xHC interrupted or another device on the shared IRQ
line interrupted. Only check the IP bit to reduce register reads.
The IP bit is automatically cleared by the xHC when MSI or MSI-X is enabled. It
doesn't make sense to read that register to check for shared interrupts (since
MSI and MSI-X aren't shared). It also doesn't make sense to write to that
register to clear the IP bit, since it is cleared by the hardware.
We can tell whether MSI or MSI-X is enabled by looking at the irq number in
hcd->irq. If it's -1, we know MSI or MSI-X is enabled.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
c21599a361