61f2e7b0f4
minix bit operations are only used by minix filesystem and useless by other modules. Because byte order of inode and block bitmaps is different on each architecture like below: m68k: big-endian 16bit indexed bitmaps h8300, microblaze, s390, sparc, m68knommu: big-endian 32 or 64bit indexed bitmaps m32r, mips, sh, xtensa: big-endian 32 or 64bit indexed bitmaps for big-endian mode little-endian bitmaps for little-endian mode Others: little-endian bitmaps In order to move minix bit operations from asm/bitops.h to architecture independent code in minix filesystem, this provides two config options. CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k. CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu, m32r, mips, sh, xtensa). The architectures which always use little-endian bitmaps do not select these options. Finally, we can remove minix bit operations from asm/bitops.h for all architectures. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Greg Ungerer <gerg@uclinux.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Andreas Schwab <schwab@linux-m68k.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Michal Simek <monstr@monstr.eu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Hirokazu Takata <takata@linux-m32r.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Paul Mundt <lethal@linux-sh.org> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
106 lines
2.4 KiB
C
106 lines
2.4 KiB
C
#ifndef __ASM_SH_BITOPS_H
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#define __ASM_SH_BITOPS_H
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#ifdef __KERNEL__
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <asm/system.h>
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/* For __swab32 */
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#include <asm/byteorder.h>
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#ifdef CONFIG_GUSA_RB
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#include <asm/bitops-grb.h>
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#elif defined(CONFIG_CPU_SH2A)
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#include <asm-generic/bitops/atomic.h>
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#include <asm/bitops-op32.h>
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#elif defined(CONFIG_CPU_SH4A)
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#include <asm/bitops-llsc.h>
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#else
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#include <asm-generic/bitops/atomic.h>
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#include <asm-generic/bitops/non-atomic.h>
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#endif
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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#ifdef CONFIG_SUPERH32
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static inline unsigned long ffz(unsigned long word)
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{
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unsigned long result;
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__asm__("1:\n\t"
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"shlr %1\n\t"
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"bt/s 1b\n\t"
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" add #1, %0"
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: "=r" (result), "=r" (word)
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: "0" (~0L), "1" (word)
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: "t");
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return result;
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}
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/**
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static inline unsigned long __ffs(unsigned long word)
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{
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unsigned long result;
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__asm__("1:\n\t"
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"shlr %1\n\t"
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"bf/s 1b\n\t"
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" add #1, %0"
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: "=r" (result), "=r" (word)
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: "0" (~0L), "1" (word)
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: "t");
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return result;
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}
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#else
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static inline unsigned long ffz(unsigned long word)
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{
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unsigned long result, __d2, __d3;
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__asm__("gettr tr0, %2\n\t"
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"pta $+32, tr0\n\t"
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"andi %1, 1, %3\n\t"
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"beq %3, r63, tr0\n\t"
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"pta $+4, tr0\n"
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"0:\n\t"
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"shlri.l %1, 1, %1\n\t"
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"addi %0, 1, %0\n\t"
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"andi %1, 1, %3\n\t"
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"beqi %3, 1, tr0\n"
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"1:\n\t"
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"ptabs %2, tr0\n\t"
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: "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
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: "0" (0L), "1" (word));
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return result;
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}
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#include <asm-generic/bitops/__ffs.h>
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#endif
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/ffs.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/fls64.h>
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_BITOPS_H */
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