edc9a958fd
Now that nommu selects 32BIT we run in to the situation where SH-2A supports an uncached identity mapping by way of the BSC, while the SH-2 does not. This provides stubs for the PC manglers and tidies up some of the system*.h mess in the process. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
#ifndef __ASM_SH_UNCACHED_H
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#define __ASM_SH_UNCACHED_H
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#include <linux/bug.h>
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#ifdef CONFIG_UNCACHED_MAPPING
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extern unsigned long cached_to_uncached;
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extern unsigned long uncached_size;
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extern unsigned long uncached_start, uncached_end;
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extern int virt_addr_uncached(unsigned long kaddr);
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extern void uncached_init(void);
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extern void uncached_resize(unsigned long size);
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/*
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* Jump to uncached area.
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* When handling TLB or caches, we need to do it from an uncached area.
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*/
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#define jump_to_uncached() \
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do { \
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unsigned long __dummy; \
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\
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__asm__ __volatile__( \
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"mova 1f, %0\n\t" \
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"add %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1:" \
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: "=&z" (__dummy) \
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: "r" (cached_to_uncached)); \
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} while (0)
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/*
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* Back to cached area.
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*/
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#define back_to_cached() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0)
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#else
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#define virt_addr_uncached(kaddr) (0)
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#define uncached_init() do { } while (0)
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#define uncached_resize(size) BUG()
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#define jump_to_uncached() do { } while (0)
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#define back_to_cached() do { } while (0)
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#endif
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#endif /* __ASM_SH_UNCACHED_H */
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