![Anson Huang](/assets/img/avatar_default.png)
During noirq suspend phase, mailbox MU irq will be masked but many drivers still need to communicate with system controller firmware via mailbox, if MU irq is masked, it will cause RPC timeout as below: [ 23.372103] imx-scu scu: RPC send msg timeout Setting MU irq to be wakeup source is NOT working as GIC driver does NOT have .irq_set_wake implemented, so to support suspend/resume, just make imx mailbox driver NOT suspend, since MU is always a wakeup source on i.MX platforms with system controller inside, and its power/clock is maintained by system controller, mailbox driver no need to manage them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
358 lines
8.3 KiB
C
358 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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/* Transmit Register */
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#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
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/* Receive Register */
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#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
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/* Status Register */
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#define IMX_MU_xSR 0x20
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#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
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#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
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#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
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#define IMX_MU_xSR_BRDIP BIT(9)
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/* Control Register */
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#define IMX_MU_xCR 0x24
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
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/* Transmit Interrupt Enable */
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#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
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/* General Purpose Interrupt Request */
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#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
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#define IMX_MU_CHANS 16
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#define IMX_MU_CHAN_NAME_SIZE 20
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enum imx_mu_chan_type {
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IMX_MU_TYPE_TX, /* Tx */
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IMX_MU_TYPE_RX, /* Rx */
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IMX_MU_TYPE_TXDB, /* Tx doorbell */
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IMX_MU_TYPE_RXDB, /* Rx doorbell */
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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enum imx_mu_chan_type type;
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struct mbox_chan *chan;
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struct tasklet_struct txdb_tasklet;
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};
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struct imx_mu_priv {
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struct device *dev;
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void __iomem *base;
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spinlock_t xcr_lock; /* control register lock */
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struct mbox_controller mbox;
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struct mbox_chan mbox_chans[IMX_MU_CHANS];
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
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struct clk *clk;
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int irq;
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bool side_b;
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};
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct imx_mu_priv, mbox);
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}
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static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
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{
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iowrite32(val, priv->base + offs);
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}
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static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
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{
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return ioread32(priv->base + offs);
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}
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static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&priv->xcr_lock, flags);
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val = imx_mu_read(priv, IMX_MU_xCR);
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val &= ~clr;
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val |= set;
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imx_mu_write(priv, val, IMX_MU_xCR);
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spin_unlock_irqrestore(&priv->xcr_lock, flags);
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return val;
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}
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static void imx_mu_txdb_tasklet(unsigned long data)
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{
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struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
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mbox_chan_txdone(cp->chan, 0);
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}
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static irqreturn_t imx_mu_isr(int irq, void *p)
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{
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struct mbox_chan *chan = p;
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 val, ctrl, dat;
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ctrl = imx_mu_read(priv, IMX_MU_xCR);
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val = imx_mu_read(priv, IMX_MU_xSR);
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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val &= IMX_MU_xSR_TEn(cp->idx) &
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(ctrl & IMX_MU_xCR_TIEn(cp->idx));
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break;
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case IMX_MU_TYPE_RX:
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val &= IMX_MU_xSR_RFn(cp->idx) &
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(ctrl & IMX_MU_xCR_RIEn(cp->idx));
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break;
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case IMX_MU_TYPE_RXDB:
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val &= IMX_MU_xSR_GIPn(cp->idx) &
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(ctrl & IMX_MU_xCR_GIEn(cp->idx));
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break;
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default:
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break;
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}
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if (!val)
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return IRQ_NONE;
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if (val == IMX_MU_xSR_TEn(cp->idx)) {
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
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mbox_chan_txdone(chan, 0);
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
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dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
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mbox_chan_received_data(chan, (void *)&dat);
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
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mbox_chan_received_data(chan, NULL);
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} else {
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dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
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return IRQ_NONE;
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}
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return IRQ_HANDLED;
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}
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static int imx_mu_send_data(struct mbox_chan *chan, void *data)
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{
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 *arg = data;
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_startup(struct mbox_chan *chan)
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{
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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int ret;
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if (cp->type == IMX_MU_TYPE_TXDB) {
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/* Tx doorbell don't have ACK support */
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tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
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(unsigned long)cp);
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return 0;
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}
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ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED |
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IRQF_NO_SUSPEND, cp->irq_desc, chan);
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if (ret) {
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dev_err(priv->dev,
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"Unable to acquire IRQ %d\n", priv->irq);
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return ret;
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}
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switch (cp->type) {
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case IMX_MU_TYPE_RX:
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
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break;
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case IMX_MU_TYPE_RXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
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break;
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default:
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break;
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}
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return 0;
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}
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static void imx_mu_shutdown(struct mbox_chan *chan)
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{
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struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
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struct imx_mu_con_priv *cp = chan->con_priv;
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if (cp->type == IMX_MU_TYPE_TXDB)
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tasklet_kill(&cp->txdb_tasklet);
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imx_mu_xcr_rmw(priv, 0,
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IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
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free_irq(priv->irq, chan);
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}
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static const struct mbox_chan_ops imx_mu_ops = {
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.send_data = imx_mu_send_data,
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.startup = imx_mu_startup,
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.shutdown = imx_mu_shutdown,
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};
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static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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{
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u32 type, idx, chan;
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if (sp->args_count != 2) {
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dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
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return ERR_PTR(-EINVAL);
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}
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type = sp->args[0]; /* channel type */
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idx = sp->args[1]; /* index */
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chan = type * 4 + idx;
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if (chan >= mbox->num_chans) {
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dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
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return ERR_PTR(-EINVAL);
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}
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return &mbox->chans[chan];
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}
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static void imx_mu_init_generic(struct imx_mu_priv *priv)
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{
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if (priv->side_b)
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return;
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/* Set default MU configuration */
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imx_mu_write(priv, 0, IMX_MU_xCR);
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}
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static int imx_mu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct resource *iomem;
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struct imx_mu_priv *priv;
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unsigned int i;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, iomem);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->irq = platform_get_irq(pdev, 0);
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if (priv->irq < 0)
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return priv->irq;
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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if (PTR_ERR(priv->clk) != -ENOENT)
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return PTR_ERR(priv->clk);
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priv->clk = NULL;
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret) {
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dev_err(dev, "Failed to enable clock\n");
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return ret;
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}
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for (i = 0; i < IMX_MU_CHANS; i++) {
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struct imx_mu_con_priv *cp = &priv->con_priv[i];
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cp->idx = i % 4;
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cp->type = i >> 2;
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cp->chan = &priv->mbox_chans[i];
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priv->mbox_chans[i].con_priv = cp;
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snprintf(cp->irq_desc, sizeof(cp->irq_desc),
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"imx_mu_chan[%i-%i]", cp->type, cp->idx);
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}
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priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
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spin_lock_init(&priv->xcr_lock);
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priv->mbox.dev = dev;
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priv->mbox.ops = &imx_mu_ops;
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priv->mbox.chans = priv->mbox_chans;
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priv->mbox.num_chans = IMX_MU_CHANS;
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priv->mbox.of_xlate = imx_mu_xlate;
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priv->mbox.txdone_irq = true;
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platform_set_drvdata(pdev, priv);
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imx_mu_init_generic(priv);
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return devm_mbox_controller_register(dev, &priv->mbox);
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}
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static int imx_mu_remove(struct platform_device *pdev)
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{
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struct imx_mu_priv *priv = platform_get_drvdata(pdev);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx6sx-mu" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
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static struct platform_driver imx_mu_driver = {
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.probe = imx_mu_probe,
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.remove = imx_mu_remove,
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.driver = {
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.name = "imx_mu",
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.of_match_table = imx_mu_dt_ids,
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},
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};
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module_platform_driver(imx_mu_driver);
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MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
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MODULE_DESCRIPTION("Message Unit driver for i.MX");
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MODULE_LICENSE("GPL v2");
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