24062fe858
HiSilicon erratum 162001800 describes the limitation of SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. On these platforms, the PMCG event counter registers (SMMU_PMCG_EVCNTRn) are read only and as a result it is not possible to set the initial counter period value on event monitor start. To work around this, the current value of the counter is read and used for delta calculations. OEM information from ACPI header is used to identify the affected hardware platforms. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [will: update silicon-errata.txt and add reason string to acpi match] Signed-off-by: Will Deacon <will.deacon@arm.com>
71 lines
2.7 KiB
C
71 lines
2.7 KiB
C
/*
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* Copyright (C) 2016, Semihalf
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* Author: Tomasz Nowicki <tn@semihalf.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*/
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#ifndef __ACPI_IORT_H__
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#define __ACPI_IORT_H__
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#include <linux/acpi.h>
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#include <linux/fwnode.h>
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#include <linux/irqdomain.h>
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#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
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#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
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/*
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* PMCG model identifiers for use in smmu pmu driver. Please note
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* that this is purely for the use of software and has nothing to
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* do with hardware or with IORT specification.
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*/
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#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
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int iort_register_domain_token(int trans_id, phys_addr_t base,
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struct fwnode_handle *fw_node);
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void iort_deregister_domain_token(int trans_id);
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struct fwnode_handle *iort_find_domain_token(int trans_id);
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#ifdef CONFIG_ACPI_IORT
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void acpi_iort_init(void);
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u32 iort_msi_map_rid(struct device *dev, u32 req_id);
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struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id);
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void acpi_configure_pmsi_domain(struct device *dev);
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int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
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/* IOMMU interface */
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void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size);
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const struct iommu_ops *iort_iommu_configure(struct device *dev);
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int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head);
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#else
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static inline void acpi_iort_init(void) { }
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static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
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{ return req_id; }
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static inline struct irq_domain *iort_get_device_domain(struct device *dev,
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u32 req_id)
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{ return NULL; }
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static inline void acpi_configure_pmsi_domain(struct device *dev) { }
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/* IOMMU interface */
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static inline void iort_dma_setup(struct device *dev, u64 *dma_addr,
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u64 *size) { }
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static inline const struct iommu_ops *iort_iommu_configure(
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struct device *dev)
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{ return NULL; }
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static inline
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int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
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{ return 0; }
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#endif
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#endif /* __ACPI_IORT_H__ */
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