34 lines
1.1 KiB
Plaintext
34 lines
1.1 KiB
Plaintext
SiFive asynchronous serial interface (UART)
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Required properties:
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- compatible: should be something similar to
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"sifive,<chip>-uart" for the UART as integrated
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on a particular chip, and "sifive,uart<version>" for the
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general UART IP block programming model. Supported
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compatible strings as of the date of this writing are:
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"sifive,fu540-c000-uart" for the SiFive UART v0 as
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integrated onto the SiFive FU540 chip, or "sifive,uart0"
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for the SiFive UART v0 IP block with no chip integration
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tweaks (if any)
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- reg: address and length of the register space
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- interrupts: Should contain the UART interrupt identifier
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- clocks: Should contain a clock identifier for the UART's parent clock
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UART HDL that corresponds to the IP block version numbers can be found
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here:
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
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Example:
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uart0: serial@10010000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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interrupt-parent = <&plic0>;
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interrupts = <80>;
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reg = <0x0 0x10010000 0x0 0x1000>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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};
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