![Rafael J. Wysocki](/assets/img/avatar_default.png)
Pull ARM cpufreq driver changes for v5.9-rc1 from Viresh Kumar: "Here are the details: - Adaptive voltage scaling (AVS) support and minor cleanups for brcmstb driver (Florian Fainelli and Markus Mayer). - A new tegra driver and cleanup for the existing one (Sumit Gupta and Jon Hunter). - Bandwidth level support for Qcom driver along with OPP changes (Sibi Sankar). - Cleanups to sti, cpufreq-dt, ap806, CPPC drivers (Viresh Kumar, Lee Jones, Ivan Kokshaysky, Sven Auhagen, and Xin Hao). - Make schedutil default governor for ARM (Valentin Schneider). - Fix dependency issues for imx (Walter Lozano). - Cleanup around cached_resolved_idx in cpufreq core (Viresh Kumar)." * 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: cpufreq: make schedutil the default for arm and arm64 cpufreq: cached_resolved_idx can not be negative cpufreq: Add Tegra194 cpufreq driver dt-bindings: arm: Add NVIDIA Tegra194 CPU Complex binding cpufreq: imx: Select NVMEM_IMX_OCOTP cpufreq: sti-cpufreq: Fix some formatting and misspelling issues cpufreq: tegra186: Simplify probe return path cpufreq: CPPC: Reuse caps variable in few routines cpufreq: ap806: fix cpufreq driver needs ap cpu clk cpufreq: cppc: Reorder code and remove apply_hisi_workaround variable cpufreq: dt: fix oops on armada37xx cpufreq: brcmstb-avs-cpufreq: send S2_ENTER / S2_EXIT commands to AVS cpufreq: brcmstb-avs-cpufreq: Support polling AVS firmware cpufreq: brcmstb-avs-cpufreq: more flexible interface for __issue_avs_command() cpufreq: qcom: Disable fast switch when scaling DDR/L3 cpufreq: qcom: Update the bandwidth levels on frequency change OPP: Add and export helper to set bandwidth cpufreq: blacklist SC7180 in cpufreq-dt-platdev cpufreq: blacklist SDM845 in cpufreq-dt-platdev
422 lines
10 KiB
C
422 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/cpufreq.h>
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#include <linux/init.h>
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#include <linux/interconnect.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#define LUT_MAX_ENTRIES 40U
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#define LUT_SRC GENMASK(31, 30)
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#define LUT_L_VAL GENMASK(7, 0)
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#define LUT_CORE_COUNT GENMASK(18, 16)
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#define LUT_VOLT GENMASK(11, 0)
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#define LUT_ROW_SIZE 32
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#define CLK_HW_DIV 2
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#define LUT_TURBO_IND 1
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/* Register offsets */
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#define REG_ENABLE 0x0
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#define REG_FREQ_LUT 0x110
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#define REG_VOLT_LUT 0x114
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#define REG_PERF_STATE 0x920
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static unsigned long cpu_hw_rate, xo_rate;
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static struct platform_device *global_pdev;
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static bool icc_scaling_enabled;
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static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
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unsigned long freq_khz)
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{
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unsigned long freq_hz = freq_khz * 1000;
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struct dev_pm_opp *opp;
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struct device *dev;
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int ret;
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dev = get_cpu_device(policy->cpu);
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if (!dev)
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return -ENODEV;
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opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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ret = dev_pm_opp_set_bw(dev, opp);
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dev_pm_opp_put(opp);
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return ret;
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}
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static int qcom_cpufreq_update_opp(struct device *cpu_dev,
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unsigned long freq_khz,
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unsigned long volt)
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{
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unsigned long freq_hz = freq_khz * 1000;
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int ret;
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/* Skip voltage update if the opp table is not available */
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if (!icc_scaling_enabled)
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return dev_pm_opp_add(cpu_dev, freq_hz, volt);
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ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
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if (ret) {
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dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
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return ret;
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}
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return dev_pm_opp_enable(cpu_dev, freq_hz);
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}
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static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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unsigned int index)
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{
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void __iomem *perf_state_reg = policy->driver_data;
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unsigned long freq = policy->freq_table[index].frequency;
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writel_relaxed(index, perf_state_reg);
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if (icc_scaling_enabled)
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qcom_cpufreq_set_bw(policy, freq);
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arch_set_freq_scale(policy->related_cpus, freq,
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policy->cpuinfo.max_freq);
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return 0;
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}
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static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
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{
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void __iomem *perf_state_reg;
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struct cpufreq_policy *policy;
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unsigned int index;
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policy = cpufreq_cpu_get_raw(cpu);
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if (!policy)
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return 0;
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perf_state_reg = policy->driver_data;
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index = readl_relaxed(perf_state_reg);
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index = min(index, LUT_MAX_ENTRIES - 1);
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return policy->freq_table[index].frequency;
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}
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static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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{
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void __iomem *perf_state_reg = policy->driver_data;
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unsigned int index;
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unsigned long freq;
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index = policy->cached_resolved_idx;
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writel_relaxed(index, perf_state_reg);
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freq = policy->freq_table[index].frequency;
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arch_set_freq_scale(policy->related_cpus, freq,
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policy->cpuinfo.max_freq);
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return freq;
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}
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static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
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struct cpufreq_policy *policy,
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void __iomem *base)
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{
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u32 data, src, lval, i, core_count, prev_freq = 0, freq;
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u32 volt;
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struct cpufreq_frequency_table *table;
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struct dev_pm_opp *opp;
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unsigned long rate;
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int ret;
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table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
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if (!table)
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return -ENOMEM;
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (!ret) {
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/* Disable all opps and cross-validate against LUT later */
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icc_scaling_enabled = true;
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for (rate = 0; ; rate++) {
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
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if (IS_ERR(opp))
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break;
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dev_pm_opp_put(opp);
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dev_pm_opp_disable(cpu_dev, rate);
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}
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} else if (ret != -ENODEV) {
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dev_err(cpu_dev, "Invalid opp table in device tree\n");
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return ret;
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} else {
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policy->fast_switch_possible = true;
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icc_scaling_enabled = false;
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}
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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data = readl_relaxed(base + REG_FREQ_LUT +
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i * LUT_ROW_SIZE);
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src = FIELD_GET(LUT_SRC, data);
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lval = FIELD_GET(LUT_L_VAL, data);
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core_count = FIELD_GET(LUT_CORE_COUNT, data);
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data = readl_relaxed(base + REG_VOLT_LUT +
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i * LUT_ROW_SIZE);
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volt = FIELD_GET(LUT_VOLT, data) * 1000;
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if (src)
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freq = xo_rate * lval / 1000;
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else
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freq = cpu_hw_rate / 1000;
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if (freq != prev_freq && core_count != LUT_TURBO_IND) {
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table[i].frequency = freq;
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qcom_cpufreq_update_opp(cpu_dev, freq, volt);
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dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
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freq, core_count);
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} else if (core_count == LUT_TURBO_IND) {
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table[i].frequency = CPUFREQ_ENTRY_INVALID;
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}
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/*
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* Two of the same frequencies with the same core counts means
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* end of table
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*/
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if (i > 0 && prev_freq == freq) {
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struct cpufreq_frequency_table *prev = &table[i - 1];
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/*
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* Only treat the last frequency that might be a boost
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* as the boost frequency
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*/
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if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
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prev->frequency = prev_freq;
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prev->flags = CPUFREQ_BOOST_FREQ;
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qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt);
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}
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break;
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}
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prev_freq = freq;
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}
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table[i].frequency = CPUFREQ_TABLE_END;
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policy->freq_table = table;
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dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
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return 0;
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}
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static void qcom_get_related_cpus(int index, struct cpumask *m)
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{
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struct device_node *cpu_np;
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struct of_phandle_args args;
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int cpu, ret;
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for_each_possible_cpu(cpu) {
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cpu_np = of_cpu_device_node_get(cpu);
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if (!cpu_np)
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continue;
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0,
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&args);
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of_node_put(cpu_np);
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if (ret < 0)
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continue;
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if (index == args.args[0])
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cpumask_set_cpu(cpu, m);
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}
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}
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static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
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{
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struct device *dev = &global_pdev->dev;
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struct of_phandle_args args;
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struct device_node *cpu_np;
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struct device *cpu_dev;
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struct resource *res;
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void __iomem *base;
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int ret, index;
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cpu_dev = get_cpu_device(policy->cpu);
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if (!cpu_dev) {
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pr_err("%s: failed to get cpu%d device\n", __func__,
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policy->cpu);
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return -ENODEV;
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}
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cpu_np = of_cpu_device_node_get(policy->cpu);
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if (!cpu_np)
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return -EINVAL;
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0, &args);
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of_node_put(cpu_np);
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if (ret)
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return ret;
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index = args.args[0];
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res = platform_get_resource(global_pdev, IORESOURCE_MEM, index);
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if (!res)
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return -ENODEV;
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base = devm_ioremap(dev, res->start, resource_size(res));
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if (!base)
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return -ENOMEM;
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/* HW should be in enabled state to proceed */
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if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
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dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
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ret = -ENODEV;
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goto error;
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}
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qcom_get_related_cpus(index, policy->cpus);
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if (!cpumask_weight(policy->cpus)) {
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dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
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ret = -ENOENT;
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goto error;
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}
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policy->driver_data = base + REG_PERF_STATE;
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ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
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if (ret) {
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dev_err(dev, "Domain-%d failed to read LUT\n", index);
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goto error;
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}
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ret = dev_pm_opp_get_opp_count(cpu_dev);
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if (ret <= 0) {
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dev_err(cpu_dev, "Failed to add OPPs\n");
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ret = -ENODEV;
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goto error;
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}
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dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
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return 0;
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error:
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devm_iounmap(dev, base);
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return ret;
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}
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static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
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{
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struct device *cpu_dev = get_cpu_device(policy->cpu);
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void __iomem *base = policy->driver_data - REG_PERF_STATE;
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dev_pm_opp_remove_all_dynamic(cpu_dev);
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dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
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kfree(policy->freq_table);
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devm_iounmap(&global_pdev->dev, base);
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return 0;
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}
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static struct freq_attr *qcom_cpufreq_hw_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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&cpufreq_freq_attr_scaling_boost_freqs,
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NULL
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};
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static struct cpufreq_driver cpufreq_qcom_hw_driver = {
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
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CPUFREQ_IS_COOLING_DEV,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = qcom_cpufreq_hw_target_index,
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.get = qcom_cpufreq_hw_get,
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.init = qcom_cpufreq_hw_cpu_init,
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.exit = qcom_cpufreq_hw_cpu_exit,
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.fast_switch = qcom_cpufreq_hw_fast_switch,
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.name = "qcom-cpufreq-hw",
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.attr = qcom_cpufreq_hw_attr,
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};
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static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
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{
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struct device *cpu_dev;
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struct clk *clk;
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int ret;
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clk = clk_get(&pdev->dev, "xo");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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xo_rate = clk_get_rate(clk);
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clk_put(clk);
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clk = clk_get(&pdev->dev, "alternate");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
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clk_put(clk);
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global_pdev = pdev;
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/* Check for optional interconnect paths on CPU0 */
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev)
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return -EPROBE_DEFER;
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ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
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if (ret)
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return ret;
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ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
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if (ret)
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dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
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else
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dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
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return ret;
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}
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static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
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{
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return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
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}
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static const struct of_device_id qcom_cpufreq_hw_match[] = {
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{ .compatible = "qcom,cpufreq-hw" },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
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static struct platform_driver qcom_cpufreq_hw_driver = {
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.probe = qcom_cpufreq_hw_driver_probe,
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.remove = qcom_cpufreq_hw_driver_remove,
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.driver = {
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.name = "qcom-cpufreq-hw",
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.of_match_table = qcom_cpufreq_hw_match,
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},
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};
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static int __init qcom_cpufreq_hw_init(void)
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{
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return platform_driver_register(&qcom_cpufreq_hw_driver);
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}
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postcore_initcall(qcom_cpufreq_hw_init);
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static void __exit qcom_cpufreq_hw_exit(void)
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{
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platform_driver_unregister(&qcom_cpufreq_hw_driver);
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}
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module_exit(qcom_cpufreq_hw_exit);
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MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
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MODULE_LICENSE("GPL v2");
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