7102e23288
This patch adds a helper function to fetch the max clock from the voltage clock dependecy tables. Clocks above that level tend to be unstable and will require additional driver tweaks in order to work properly. This patch implemented the helper function to fetch the max clocks from the dependency tables. The following patches implement the per-asic clock filtering. See bug: https://bugs.freedesktop.org/show_bug.cgi?id=68235 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
60 lines
2.8 KiB
C
60 lines
2.8 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __BTC_DPM_H__
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#define __BTC_DPM_H__
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#define BTC_RLP_UVD_DFLT 20
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#define BTC_RMP_UVD_DFLT 50
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#define BTC_LHP_UVD_DFLT 50
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#define BTC_LMP_UVD_DFLT 20
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#define BARTS_MGCGCGTSSMCTRL_DFLT 0x81944000
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#define TURKS_MGCGCGTSSMCTRL_DFLT 0x6e944000
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#define CAICOS_MGCGCGTSSMCTRL_DFLT 0x46944040
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#define BTC_CGULVPARAMETER_DFLT 0x00040035
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#define BTC_CGULVCONTROL_DFLT 0x00001450
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extern u32 btc_valid_sclk[40];
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void btc_read_arb_registers(struct radeon_device *rdev);
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void btc_program_mgcg_hw_sequence(struct radeon_device *rdev,
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const u32 *sequence, u32 count);
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void btc_skip_blacklist_clocks(struct radeon_device *rdev,
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const u32 max_sclk, const u32 max_mclk,
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u32 *sclk, u32 *mclk);
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void btc_adjust_clock_combinations(struct radeon_device *rdev,
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const struct radeon_clock_and_voltage_limits *max_limits,
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struct rv7xx_pl *pl);
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void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
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u32 clock, u16 max_voltage, u16 *voltage);
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void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
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u32 *max_clock);
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void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
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u16 max_vddc, u16 max_vddci,
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u16 *vddc, u16 *vddci);
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bool btc_dpm_enabled(struct radeon_device *rdev);
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int btc_reset_to_default(struct radeon_device *rdev);
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void btc_notify_uvd_to_smc(struct radeon_device *rdev,
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struct radeon_ps *radeon_new_state);
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#endif
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