2ce529dac7
For powergating, we just need to re-init the registers, there is no need to restore the uvd BOs. This just adds needless work when powergating uvd for playback while the system is on. We only need to restore the uvd BOs on an actual resume from suspend or when the driver loads. This fixes multi-stream UVD playback on KB systems. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "cikd.h"
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/**
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* uvd_v4_2_resume - memory controller programming
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*
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* @rdev: radeon_device pointer
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*
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* Let the UVD memory controller know it's offsets
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*/
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int uvd_v4_2_resume(struct radeon_device *rdev)
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{
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uint64_t addr;
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uint32_t size;
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/* programm the VCPU memory controller bits 0-27 */
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addr = rdev->uvd.gpu_addr >> 3;
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size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
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WREG32(UVD_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = RADEON_UVD_STACK_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
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WREG32(UVD_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = RADEON_UVD_HEAP_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
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WREG32(UVD_VCPU_CACHE_SIZE2, size);
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/* bits 28-31 */
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addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
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WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
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/* bits 32-39 */
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addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
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return 0;
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}
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