![Linus Walleij](/assets/img/avatar_default.png)
The MCDE DSI link hardware which is modeled like a bridge in DRM, connected further to the panel bridge, creating a pipeline. We have been using the .pre_enable(), .enable(), .disable() and .post_disable() callbacks from the bridge to set this up in a chained manner: first the display controller goes online and then in successive order each bridge in the pipeline. Inside DRM it works like this: drm_atomic_helper_commit_tail() drm_atomic_helper_commit_modeset_enables() struct drm_crtc_helper_funcs .atomic_enable() struct drm_simple_display_pipe_funcs .enable() MCDE display enable call drm_atomic_bridge_chain_enable() struct drm_bridge_funcs .pre_enable() mcde_dsi_bridge_pre_enable() panel_bridge_pre_enable() struct drm_panel_funcs .prepare() struct drm_bridge_funcs .enable() mcde_dsi_bridge_enable() panel_bridge_enable() struct drm_panel_funcs .enable() A similar sequence is executed for disabling. Unfortunately this is not what the hardware needs: at a certain stage in the enablement of the display controller the DSI link needs to come up to support video mode, else something (like a FIFO flow) locks up the hardware and we never get picture. Fix this by simply leaving the pre|enable and post|disable callbacks unused, and establish two cross-calls from the display controller to bring up the DSI link at the right place in the display bring-up sequence and vice versa in the shutdown sequence. For command mode displays, it works just fine to also enable the display flow early. The only time we hold it back right now is in one-shot mode, on-demand display updates. When combined with the previous patch and some patches for the S6E63M0 display controller to support DSI mode, this gives working display on the Samsung GT-I8190 (Golden) phone. It has also been tested working on the Samsung GT-S7710 (Skomer) phone. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: newbytee@protonmail.com Cc: Stephan Gerhold <stephan@gerhold.net> Link: https://patchwork.freedesktop.org/patch/msgid/20200808223122.1492124-4-linus.walleij@linaro.org
1275 lines
32 KiB
C
1275 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org>
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* Parts of this file were based on the MCDE driver by Marcus Lorentzon
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* (C) ST-Ericsson SA 2013
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-buf.h>
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#include <linux/regulator/consumer.h>
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#include <drm/drm_device.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_simple_kms_helper.h>
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#include <drm/drm_vblank.h>
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#include <video/mipi_display.h>
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#include "mcde_drm.h"
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#include "mcde_display_regs.h"
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enum mcde_fifo {
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MCDE_FIFO_A,
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MCDE_FIFO_B,
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/* TODO: implement FIFO C0 and FIFO C1 */
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};
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enum mcde_channel {
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MCDE_CHANNEL_0 = 0,
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MCDE_CHANNEL_1,
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MCDE_CHANNEL_2,
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MCDE_CHANNEL_3,
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};
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enum mcde_extsrc {
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MCDE_EXTSRC_0 = 0,
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MCDE_EXTSRC_1,
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MCDE_EXTSRC_2,
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MCDE_EXTSRC_3,
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MCDE_EXTSRC_4,
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MCDE_EXTSRC_5,
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MCDE_EXTSRC_6,
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MCDE_EXTSRC_7,
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MCDE_EXTSRC_8,
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MCDE_EXTSRC_9,
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};
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enum mcde_overlay {
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MCDE_OVERLAY_0 = 0,
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MCDE_OVERLAY_1,
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MCDE_OVERLAY_2,
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MCDE_OVERLAY_3,
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MCDE_OVERLAY_4,
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MCDE_OVERLAY_5,
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};
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enum mcde_dsi_formatter {
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MCDE_DSI_FORMATTER_0 = 0,
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MCDE_DSI_FORMATTER_1,
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MCDE_DSI_FORMATTER_2,
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};
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void mcde_display_irq(struct mcde *mcde)
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{
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u32 mispp, misovl, mischnl;
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bool vblank = false;
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/* Handle display IRQs */
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mispp = readl(mcde->regs + MCDE_MISPP);
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misovl = readl(mcde->regs + MCDE_MISOVL);
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mischnl = readl(mcde->regs + MCDE_MISCHNL);
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/*
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* Handle IRQs from the DSI link. All IRQs from the DSI links
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* are just latched onto the MCDE IRQ line, so we need to traverse
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* any active DSI masters and check if an IRQ is originating from
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* them.
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*
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* TODO: Currently only one DSI link is supported.
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*/
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if (mcde_dsi_irq(mcde->mdsi)) {
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u32 val;
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/*
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* In oneshot mode we do not send continuous updates
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* to the display, instead we only push out updates when
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* the update function is called, then we disable the
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* flow on the channel once we get the TE IRQ.
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*/
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if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
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spin_lock(&mcde->flow_lock);
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if (--mcde->flow_active == 0) {
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dev_dbg(mcde->dev, "TE0 IRQ\n");
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/* Disable FIFO A flow */
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val = readl(mcde->regs + MCDE_CRA0);
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val &= ~MCDE_CRX0_FLOEN;
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writel(val, mcde->regs + MCDE_CRA0);
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}
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spin_unlock(&mcde->flow_lock);
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}
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}
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/* Vblank from one of the channels */
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if (mispp & MCDE_PP_VCMPA) {
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dev_dbg(mcde->dev, "chnl A vblank IRQ\n");
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vblank = true;
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}
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if (mispp & MCDE_PP_VCMPB) {
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dev_dbg(mcde->dev, "chnl B vblank IRQ\n");
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vblank = true;
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}
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if (mispp & MCDE_PP_VCMPC0)
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dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n");
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if (mispp & MCDE_PP_VCMPC1)
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dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n");
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if (mispp & MCDE_PP_VSCC0)
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dev_dbg(mcde->dev, "chnl C0 TE IRQ\n");
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if (mispp & MCDE_PP_VSCC1)
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dev_dbg(mcde->dev, "chnl C1 TE IRQ\n");
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writel(mispp, mcde->regs + MCDE_RISPP);
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if (vblank)
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drm_crtc_handle_vblank(&mcde->pipe.crtc);
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if (misovl)
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dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl);
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writel(misovl, mcde->regs + MCDE_RISOVL);
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if (mischnl)
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dev_info(mcde->dev, "some stray channel error IRQ %08x\n",
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mischnl);
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writel(mischnl, mcde->regs + MCDE_RISCHNL);
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}
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void mcde_display_disable_irqs(struct mcde *mcde)
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{
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/* Disable all IRQs */
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writel(0, mcde->regs + MCDE_IMSCPP);
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writel(0, mcde->regs + MCDE_IMSCOVL);
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writel(0, mcde->regs + MCDE_IMSCCHNL);
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/* Clear any pending IRQs */
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writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
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writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);
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writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);
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}
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static int mcde_display_check(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *pstate,
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struct drm_crtc_state *cstate)
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{
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const struct drm_display_mode *mode = &cstate->mode;
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struct drm_framebuffer *old_fb = pipe->plane.state->fb;
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struct drm_framebuffer *fb = pstate->fb;
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if (fb) {
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u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
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/* FB base address must be dword aligned. */
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if (offset & 3) {
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DRM_DEBUG_KMS("FB not 32-bit aligned\n");
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return -EINVAL;
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}
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/*
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* There's no pitch register, the mode's hdisplay
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* controls this.
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*/
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if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) {
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DRM_DEBUG_KMS("can't handle pitches\n");
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return -EINVAL;
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}
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/*
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* We can't change the FB format in a flicker-free
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* manner (and only update it during CRTC enable).
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*/
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if (old_fb && old_fb->format != fb->format)
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cstate->mode_changed = true;
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}
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return 0;
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}
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static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src,
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u32 format)
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{
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u32 val;
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u32 conf;
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u32 cr;
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switch (src) {
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case MCDE_EXTSRC_0:
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conf = MCDE_EXTSRC0CONF;
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cr = MCDE_EXTSRC0CR;
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break;
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case MCDE_EXTSRC_1:
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conf = MCDE_EXTSRC1CONF;
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cr = MCDE_EXTSRC1CR;
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break;
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case MCDE_EXTSRC_2:
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conf = MCDE_EXTSRC2CONF;
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cr = MCDE_EXTSRC2CR;
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break;
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case MCDE_EXTSRC_3:
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conf = MCDE_EXTSRC3CONF;
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cr = MCDE_EXTSRC3CR;
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break;
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case MCDE_EXTSRC_4:
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conf = MCDE_EXTSRC4CONF;
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cr = MCDE_EXTSRC4CR;
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break;
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case MCDE_EXTSRC_5:
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conf = MCDE_EXTSRC5CONF;
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cr = MCDE_EXTSRC5CR;
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break;
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case MCDE_EXTSRC_6:
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conf = MCDE_EXTSRC6CONF;
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cr = MCDE_EXTSRC6CR;
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break;
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case MCDE_EXTSRC_7:
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conf = MCDE_EXTSRC7CONF;
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cr = MCDE_EXTSRC7CR;
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break;
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case MCDE_EXTSRC_8:
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conf = MCDE_EXTSRC8CONF;
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cr = MCDE_EXTSRC8CR;
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break;
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case MCDE_EXTSRC_9:
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conf = MCDE_EXTSRC9CONF;
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cr = MCDE_EXTSRC9CR;
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break;
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}
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/*
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* Configure external source 0 one buffer (buffer 0)
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* primary overlay ID 0.
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* From mcde_hw.c ovly_update_registers() in the vendor tree
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*/
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val = 0 << MCDE_EXTSRCXCONF_BUF_ID_SHIFT;
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val |= 1 << MCDE_EXTSRCXCONF_BUF_NB_SHIFT;
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val |= 0 << MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT;
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/*
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* MCDE has inverse semantics from DRM on RBG/BGR which is why
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* all the modes are inversed here.
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*/
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switch (format) {
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case DRM_FORMAT_ARGB8888:
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val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_ABGR8888:
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val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_XRGB8888:
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val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_XBGR8888:
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val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_RGB888:
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val |= MCDE_EXTSRCXCONF_BPP_RGB888 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_BGR888:
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val |= MCDE_EXTSRCXCONF_BPP_RGB888 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_ARGB4444:
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val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_ABGR4444:
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val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_XRGB4444:
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val |= MCDE_EXTSRCXCONF_BPP_RGB444 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_XBGR4444:
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val |= MCDE_EXTSRCXCONF_BPP_RGB444 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_XRGB1555:
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val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_XBGR1555:
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val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_RGB565:
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val |= MCDE_EXTSRCXCONF_BPP_RGB565 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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val |= MCDE_EXTSRCXCONF_BGR;
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break;
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case DRM_FORMAT_BGR565:
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val |= MCDE_EXTSRCXCONF_BPP_RGB565 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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case DRM_FORMAT_YUV422:
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val |= MCDE_EXTSRCXCONF_BPP_YCBCR422 <<
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MCDE_EXTSRCXCONF_BPP_SHIFT;
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break;
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default:
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dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
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format);
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return -EINVAL;
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}
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writel(val, mcde->regs + conf);
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/* Software select, primary */
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val = MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL;
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val |= MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY;
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writel(val, mcde->regs + cr);
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return 0;
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}
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static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl,
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enum mcde_extsrc src,
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enum mcde_channel ch,
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const struct drm_display_mode *mode,
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u32 format, int cpp)
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{
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u32 val;
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u32 conf1;
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u32 conf2;
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u32 crop;
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u32 ljinc;
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u32 cr;
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u32 comp;
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u32 pixel_fetcher_watermark;
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switch (ovl) {
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case MCDE_OVERLAY_0:
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conf1 = MCDE_OVL0CONF;
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conf2 = MCDE_OVL0CONF2;
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crop = MCDE_OVL0CROP;
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ljinc = MCDE_OVL0LJINC;
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cr = MCDE_OVL0CR;
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comp = MCDE_OVL0COMP;
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break;
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case MCDE_OVERLAY_1:
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conf1 = MCDE_OVL1CONF;
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conf2 = MCDE_OVL1CONF2;
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crop = MCDE_OVL1CROP;
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ljinc = MCDE_OVL1LJINC;
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cr = MCDE_OVL1CR;
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comp = MCDE_OVL1COMP;
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break;
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case MCDE_OVERLAY_2:
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conf1 = MCDE_OVL2CONF;
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conf2 = MCDE_OVL2CONF2;
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crop = MCDE_OVL2CROP;
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ljinc = MCDE_OVL2LJINC;
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cr = MCDE_OVL2CR;
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comp = MCDE_OVL2COMP;
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break;
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case MCDE_OVERLAY_3:
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conf1 = MCDE_OVL3CONF;
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conf2 = MCDE_OVL3CONF2;
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crop = MCDE_OVL3CROP;
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ljinc = MCDE_OVL3LJINC;
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cr = MCDE_OVL3CR;
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comp = MCDE_OVL3COMP;
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break;
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case MCDE_OVERLAY_4:
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conf1 = MCDE_OVL4CONF;
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conf2 = MCDE_OVL4CONF2;
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crop = MCDE_OVL4CROP;
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ljinc = MCDE_OVL4LJINC;
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cr = MCDE_OVL4CR;
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comp = MCDE_OVL4COMP;
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break;
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case MCDE_OVERLAY_5:
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conf1 = MCDE_OVL5CONF;
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conf2 = MCDE_OVL5CONF2;
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crop = MCDE_OVL5CROP;
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ljinc = MCDE_OVL5LJINC;
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cr = MCDE_OVL5CR;
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comp = MCDE_OVL5COMP;
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break;
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}
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val = mode->hdisplay << MCDE_OVLXCONF_PPL_SHIFT;
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val |= mode->vdisplay << MCDE_OVLXCONF_LPF_SHIFT;
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/* Use external source 0 that we just configured */
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val |= src << MCDE_OVLXCONF_EXTSRC_ID_SHIFT;
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writel(val, mcde->regs + conf1);
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val = MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA;
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val |= 0xff << MCDE_OVLXCONF2_ALPHAVALUE_SHIFT;
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/* OPQ: overlay is opaque */
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switch (format) {
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_ARGB4444:
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case DRM_FORMAT_ABGR4444:
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case DRM_FORMAT_XRGB1555:
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case DRM_FORMAT_XBGR1555:
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/* No OPQ */
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break;
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_BGR888:
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_BGR565:
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case DRM_FORMAT_YUV422:
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val |= MCDE_OVLXCONF2_OPQ;
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break;
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default:
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dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
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format);
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break;
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}
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/*
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* Pixel fetch watermark level is max 0x1FFF pixels.
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* Two basic rules should be followed:
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* 1. The value should be at least 256 bits.
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* 2. The sum of all active overlays pixelfetch watermark level
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* multiplied with bits per pixel, should be lower than the
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* size of input_fifo_size in bits.
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* 3. The value should be a multiple of a line (256 bits).
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*/
|
|
switch (cpp) {
|
|
case 2:
|
|
pixel_fetcher_watermark = 128;
|
|
break;
|
|
case 3:
|
|
pixel_fetcher_watermark = 96;
|
|
break;
|
|
case 4:
|
|
pixel_fetcher_watermark = 48;
|
|
break;
|
|
default:
|
|
pixel_fetcher_watermark = 48;
|
|
break;
|
|
}
|
|
dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n",
|
|
pixel_fetcher_watermark);
|
|
val |= pixel_fetcher_watermark << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT;
|
|
writel(val, mcde->regs + conf2);
|
|
|
|
/* Number of bytes to fetch per line */
|
|
writel(mcde->stride, mcde->regs + ljinc);
|
|
/* No cropping */
|
|
writel(0, mcde->regs + crop);
|
|
|
|
/* Set up overlay control register */
|
|
val = MCDE_OVLXCR_OVLEN;
|
|
val |= MCDE_OVLXCR_COLCCTRL_DISABLED;
|
|
val |= MCDE_OVLXCR_BURSTSIZE_8W <<
|
|
MCDE_OVLXCR_BURSTSIZE_SHIFT;
|
|
val |= MCDE_OVLXCR_MAXOUTSTANDING_8_REQ <<
|
|
MCDE_OVLXCR_MAXOUTSTANDING_SHIFT;
|
|
/* Not using rotation but set it up anyways */
|
|
val |= MCDE_OVLXCR_ROTBURSTSIZE_8W <<
|
|
MCDE_OVLXCR_ROTBURSTSIZE_SHIFT;
|
|
writel(val, mcde->regs + cr);
|
|
|
|
/*
|
|
* Set up the overlay compositor to route the overlay out to
|
|
* the desired channel
|
|
*/
|
|
val = ch << MCDE_OVLXCOMP_CH_ID_SHIFT;
|
|
writel(val, mcde->regs + comp);
|
|
}
|
|
|
|
static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch,
|
|
enum mcde_fifo fifo,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
u32 val;
|
|
u32 conf;
|
|
u32 sync;
|
|
u32 stat;
|
|
u32 bgcol;
|
|
u32 mux;
|
|
|
|
switch (ch) {
|
|
case MCDE_CHANNEL_0:
|
|
conf = MCDE_CHNL0CONF;
|
|
sync = MCDE_CHNL0SYNCHMOD;
|
|
stat = MCDE_CHNL0STAT;
|
|
bgcol = MCDE_CHNL0BCKGNDCOL;
|
|
mux = MCDE_CHNL0MUXING;
|
|
break;
|
|
case MCDE_CHANNEL_1:
|
|
conf = MCDE_CHNL1CONF;
|
|
sync = MCDE_CHNL1SYNCHMOD;
|
|
stat = MCDE_CHNL1STAT;
|
|
bgcol = MCDE_CHNL1BCKGNDCOL;
|
|
mux = MCDE_CHNL1MUXING;
|
|
break;
|
|
case MCDE_CHANNEL_2:
|
|
conf = MCDE_CHNL2CONF;
|
|
sync = MCDE_CHNL2SYNCHMOD;
|
|
stat = MCDE_CHNL2STAT;
|
|
bgcol = MCDE_CHNL2BCKGNDCOL;
|
|
mux = MCDE_CHNL2MUXING;
|
|
break;
|
|
case MCDE_CHANNEL_3:
|
|
conf = MCDE_CHNL3CONF;
|
|
sync = MCDE_CHNL3SYNCHMOD;
|
|
stat = MCDE_CHNL3STAT;
|
|
bgcol = MCDE_CHNL3BCKGNDCOL;
|
|
mux = MCDE_CHNL3MUXING;
|
|
return;
|
|
}
|
|
|
|
/* Set up channel 0 sync (based on chnl_update_registers()) */
|
|
switch (mcde->flow_mode) {
|
|
case MCDE_COMMAND_ONESHOT_FLOW:
|
|
/* Oneshot is achieved with software sync */
|
|
val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE
|
|
<< MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
|
|
break;
|
|
case MCDE_COMMAND_TE_FLOW:
|
|
val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
|
|
<< MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
|
|
val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
|
|
<< MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
|
|
break;
|
|
case MCDE_COMMAND_BTA_TE_FLOW:
|
|
val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
|
|
<< MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
|
|
/*
|
|
* TODO:
|
|
* The vendor driver uses the formatter as sync source
|
|
* for BTA TE mode. Test to use TE if you have a panel
|
|
* that uses this mode.
|
|
*/
|
|
val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
|
|
<< MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
|
|
break;
|
|
case MCDE_VIDEO_TE_FLOW:
|
|
val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
|
|
<< MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
|
|
val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
|
|
<< MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
|
|
break;
|
|
case MCDE_VIDEO_FORMATTER_FLOW:
|
|
val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
|
|
<< MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
|
|
val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
|
|
<< MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
|
|
break;
|
|
default:
|
|
dev_err(mcde->dev, "unknown flow mode %d\n",
|
|
mcde->flow_mode);
|
|
break;
|
|
}
|
|
|
|
writel(val, mcde->regs + sync);
|
|
|
|
/* Set up pixels per line and lines per frame */
|
|
val = (mode->hdisplay - 1) << MCDE_CHNLXCONF_PPL_SHIFT;
|
|
val |= (mode->vdisplay - 1) << MCDE_CHNLXCONF_LPF_SHIFT;
|
|
writel(val, mcde->regs + conf);
|
|
|
|
/*
|
|
* Normalize color conversion:
|
|
* black background, OLED conversion disable on channel
|
|
*/
|
|
val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN |
|
|
MCDE_CHNLXSTAT_CHNLRD;
|
|
writel(val, mcde->regs + stat);
|
|
writel(0, mcde->regs + bgcol);
|
|
|
|
/* Set up muxing: connect the channel to the desired FIFO */
|
|
switch (fifo) {
|
|
case MCDE_FIFO_A:
|
|
writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_A,
|
|
mcde->regs + mux);
|
|
break;
|
|
case MCDE_FIFO_B:
|
|
writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_B,
|
|
mcde->regs + mux);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo,
|
|
enum mcde_dsi_formatter fmt,
|
|
int fifo_wtrmrk)
|
|
{
|
|
u32 val;
|
|
u32 ctrl;
|
|
u32 cr0, cr1;
|
|
|
|
switch (fifo) {
|
|
case MCDE_FIFO_A:
|
|
ctrl = MCDE_CTRLA;
|
|
cr0 = MCDE_CRA0;
|
|
cr1 = MCDE_CRA1;
|
|
break;
|
|
case MCDE_FIFO_B:
|
|
ctrl = MCDE_CTRLB;
|
|
cr0 = MCDE_CRB0;
|
|
cr1 = MCDE_CRB1;
|
|
break;
|
|
}
|
|
|
|
val = fifo_wtrmrk << MCDE_CTRLX_FIFOWTRMRK_SHIFT;
|
|
/* We only support DSI formatting for now */
|
|
val |= MCDE_CTRLX_FORMTYPE_DSI <<
|
|
MCDE_CTRLX_FORMTYPE_SHIFT;
|
|
|
|
/* Select the formatter to use for this FIFO */
|
|
val |= fmt << MCDE_CTRLX_FORMID_SHIFT;
|
|
writel(val, mcde->regs + ctrl);
|
|
|
|
/* Blend source with Alpha 0xff on FIFO */
|
|
val = MCDE_CRX0_BLENDEN |
|
|
0xff << MCDE_CRX0_ALPHABLEND_SHIFT;
|
|
writel(val, mcde->regs + cr0);
|
|
|
|
/* Set-up from mcde_fmtr_dsi.c, fmtr_dsi_enable_video() */
|
|
|
|
/* Use the MCDE clock for this FIFO */
|
|
val = MCDE_CRX1_CLKSEL_MCDECLK << MCDE_CRX1_CLKSEL_SHIFT;
|
|
|
|
/* TODO: when adding DPI support add OUTBPP etc here */
|
|
writel(val, mcde->regs + cr1);
|
|
};
|
|
|
|
static void mcde_configure_dsi_formatter(struct mcde *mcde,
|
|
enum mcde_dsi_formatter fmt,
|
|
u32 formatter_frame,
|
|
int pkt_size)
|
|
{
|
|
u32 val;
|
|
u32 conf0;
|
|
u32 frame;
|
|
u32 pkt;
|
|
u32 sync;
|
|
u32 cmdw;
|
|
u32 delay0, delay1;
|
|
|
|
switch (fmt) {
|
|
case MCDE_DSI_FORMATTER_0:
|
|
conf0 = MCDE_DSIVID0CONF0;
|
|
frame = MCDE_DSIVID0FRAME;
|
|
pkt = MCDE_DSIVID0PKT;
|
|
sync = MCDE_DSIVID0SYNC;
|
|
cmdw = MCDE_DSIVID0CMDW;
|
|
delay0 = MCDE_DSIVID0DELAY0;
|
|
delay1 = MCDE_DSIVID0DELAY1;
|
|
break;
|
|
case MCDE_DSI_FORMATTER_1:
|
|
conf0 = MCDE_DSIVID1CONF0;
|
|
frame = MCDE_DSIVID1FRAME;
|
|
pkt = MCDE_DSIVID1PKT;
|
|
sync = MCDE_DSIVID1SYNC;
|
|
cmdw = MCDE_DSIVID1CMDW;
|
|
delay0 = MCDE_DSIVID1DELAY0;
|
|
delay1 = MCDE_DSIVID1DELAY1;
|
|
break;
|
|
case MCDE_DSI_FORMATTER_2:
|
|
conf0 = MCDE_DSIVID2CONF0;
|
|
frame = MCDE_DSIVID2FRAME;
|
|
pkt = MCDE_DSIVID2PKT;
|
|
sync = MCDE_DSIVID2SYNC;
|
|
cmdw = MCDE_DSIVID2CMDW;
|
|
delay0 = MCDE_DSIVID2DELAY0;
|
|
delay1 = MCDE_DSIVID2DELAY1;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Enable formatter
|
|
* 8 bit commands and DCS commands (notgen = not generic)
|
|
*/
|
|
val = MCDE_DSICONF0_CMD8 | MCDE_DSICONF0_DCSVID_NOTGEN;
|
|
if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
|
|
val |= MCDE_DSICONF0_VID_MODE_VID;
|
|
switch (mcde->mdsi->format) {
|
|
case MIPI_DSI_FMT_RGB888:
|
|
val |= MCDE_DSICONF0_PACKING_RGB888 <<
|
|
MCDE_DSICONF0_PACKING_SHIFT;
|
|
break;
|
|
case MIPI_DSI_FMT_RGB666:
|
|
val |= MCDE_DSICONF0_PACKING_RGB666 <<
|
|
MCDE_DSICONF0_PACKING_SHIFT;
|
|
break;
|
|
case MIPI_DSI_FMT_RGB666_PACKED:
|
|
val |= MCDE_DSICONF0_PACKING_RGB666_PACKED <<
|
|
MCDE_DSICONF0_PACKING_SHIFT;
|
|
break;
|
|
case MIPI_DSI_FMT_RGB565:
|
|
val |= MCDE_DSICONF0_PACKING_RGB565 <<
|
|
MCDE_DSICONF0_PACKING_SHIFT;
|
|
break;
|
|
default:
|
|
dev_err(mcde->dev, "unknown DSI format\n");
|
|
return;
|
|
}
|
|
writel(val, mcde->regs + conf0);
|
|
|
|
writel(formatter_frame, mcde->regs + frame);
|
|
writel(pkt_size, mcde->regs + pkt);
|
|
writel(0, mcde->regs + sync);
|
|
/* Define the MIPI command: we want to write into display memory */
|
|
val = MIPI_DCS_WRITE_MEMORY_CONTINUE <<
|
|
MCDE_DSIVIDXCMDW_CMDW_CONTINUE_SHIFT;
|
|
val |= MIPI_DCS_WRITE_MEMORY_START <<
|
|
MCDE_DSIVIDXCMDW_CMDW_START_SHIFT;
|
|
writel(val, mcde->regs + cmdw);
|
|
|
|
/*
|
|
* FIXME: the vendor driver has some hack around this value in
|
|
* CMD mode with autotrig.
|
|
*/
|
|
writel(0, mcde->regs + delay0);
|
|
writel(0, mcde->regs + delay1);
|
|
}
|
|
|
|
static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo)
|
|
{
|
|
u32 val;
|
|
u32 cr;
|
|
|
|
switch (fifo) {
|
|
case MCDE_FIFO_A:
|
|
cr = MCDE_CRA0;
|
|
break;
|
|
case MCDE_FIFO_B:
|
|
cr = MCDE_CRB0;
|
|
break;
|
|
default:
|
|
dev_err(mcde->dev, "cannot enable FIFO %c\n",
|
|
'A' + fifo);
|
|
return;
|
|
}
|
|
|
|
spin_lock(&mcde->flow_lock);
|
|
val = readl(mcde->regs + cr);
|
|
val |= MCDE_CRX0_FLOEN;
|
|
writel(val, mcde->regs + cr);
|
|
mcde->flow_active++;
|
|
spin_unlock(&mcde->flow_lock);
|
|
}
|
|
|
|
static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo,
|
|
bool wait_for_drain)
|
|
{
|
|
int timeout = 100;
|
|
u32 val;
|
|
u32 cr;
|
|
|
|
switch (fifo) {
|
|
case MCDE_FIFO_A:
|
|
cr = MCDE_CRA0;
|
|
break;
|
|
case MCDE_FIFO_B:
|
|
cr = MCDE_CRB0;
|
|
break;
|
|
default:
|
|
dev_err(mcde->dev, "cannot disable FIFO %c\n",
|
|
'A' + fifo);
|
|
return;
|
|
}
|
|
|
|
spin_lock(&mcde->flow_lock);
|
|
val = readl(mcde->regs + cr);
|
|
val &= ~MCDE_CRX0_FLOEN;
|
|
writel(val, mcde->regs + cr);
|
|
mcde->flow_active = 0;
|
|
spin_unlock(&mcde->flow_lock);
|
|
|
|
if (!wait_for_drain)
|
|
return;
|
|
|
|
/* Check that we really drained and stopped the flow */
|
|
while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {
|
|
usleep_range(1000, 1500);
|
|
if (!--timeout) {
|
|
dev_err(mcde->dev,
|
|
"FIFO timeout while clearing FIFO %c\n",
|
|
'A' + fifo);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This drains a pipe i.e. a FIFO connected to a certain channel
|
|
*/
|
|
static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo,
|
|
enum mcde_channel ch)
|
|
{
|
|
u32 val;
|
|
u32 ctrl;
|
|
u32 synsw;
|
|
|
|
switch (fifo) {
|
|
case MCDE_FIFO_A:
|
|
ctrl = MCDE_CTRLA;
|
|
break;
|
|
case MCDE_FIFO_B:
|
|
ctrl = MCDE_CTRLB;
|
|
break;
|
|
}
|
|
|
|
switch (ch) {
|
|
case MCDE_CHANNEL_0:
|
|
synsw = MCDE_CHNL0SYNCHSW;
|
|
break;
|
|
case MCDE_CHANNEL_1:
|
|
synsw = MCDE_CHNL1SYNCHSW;
|
|
break;
|
|
case MCDE_CHANNEL_2:
|
|
synsw = MCDE_CHNL2SYNCHSW;
|
|
break;
|
|
case MCDE_CHANNEL_3:
|
|
synsw = MCDE_CHNL3SYNCHSW;
|
|
return;
|
|
}
|
|
|
|
val = readl(mcde->regs + ctrl);
|
|
if (!(val & MCDE_CTRLX_FIFOEMPTY)) {
|
|
dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n");
|
|
/* Attempt to clear the FIFO */
|
|
mcde_enable_fifo(mcde, fifo);
|
|
/* Trigger a software sync out on respective channel (0-3) */
|
|
writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);
|
|
/* Disable FIFO A flow again */
|
|
mcde_disable_fifo(mcde, fifo, true);
|
|
}
|
|
}
|
|
|
|
static int mcde_dsi_get_pkt_div(int ppl, int fifo_size)
|
|
{
|
|
/*
|
|
* DSI command mode line packets should be split into an even number of
|
|
* packets smaller than or equal to the fifo size.
|
|
*/
|
|
int div;
|
|
const int max_div = DIV_ROUND_UP(MCDE_MAX_WIDTH, fifo_size);
|
|
|
|
for (div = 1; div < max_div; div++)
|
|
if (ppl % div == 0 && ppl / div <= fifo_size)
|
|
return div;
|
|
return 1;
|
|
}
|
|
|
|
static void mcde_display_enable(struct drm_simple_display_pipe *pipe,
|
|
struct drm_crtc_state *cstate,
|
|
struct drm_plane_state *plane_state)
|
|
{
|
|
struct drm_crtc *crtc = &pipe->crtc;
|
|
struct drm_plane *plane = &pipe->plane;
|
|
struct drm_device *drm = crtc->dev;
|
|
struct mcde *mcde = to_mcde(drm);
|
|
const struct drm_display_mode *mode = &cstate->mode;
|
|
struct drm_framebuffer *fb = plane->state->fb;
|
|
u32 format = fb->format->format;
|
|
u32 formatter_ppl = mode->hdisplay; /* pixels per line */
|
|
u32 formatter_lpf = mode->vdisplay; /* lines per frame */
|
|
int pkt_size, fifo_wtrmrk;
|
|
int cpp = fb->format->cpp[0];
|
|
int formatter_cpp;
|
|
struct drm_format_name_buf tmp;
|
|
u32 formatter_frame;
|
|
u32 pkt_div;
|
|
u32 val;
|
|
int ret;
|
|
|
|
/* This powers up the entire MCDE block and the DSI hardware */
|
|
ret = regulator_enable(mcde->epod);
|
|
if (ret) {
|
|
dev_err(drm->dev, "can't re-enable EPOD regulator\n");
|
|
return;
|
|
}
|
|
|
|
dev_info(drm->dev, "enable MCDE, %d x %d format %s\n",
|
|
mode->hdisplay, mode->vdisplay,
|
|
drm_get_format_name(format, &tmp));
|
|
if (!mcde->mdsi) {
|
|
/* TODO: deal with this for non-DSI output */
|
|
dev_err(drm->dev, "no DSI master attached!\n");
|
|
return;
|
|
}
|
|
|
|
/* Set up the main control, watermark level at 7 */
|
|
val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT;
|
|
/* 24 bits DPI: connect LSB Ch B to D[0:7] */
|
|
val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT;
|
|
/* TV out: connect LSB Ch B to D[8:15] */
|
|
val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT;
|
|
/* Don't care about this muxing */
|
|
val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT;
|
|
/* 24 bits DPI: connect MID Ch B to D[24:31] */
|
|
val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT;
|
|
/* 5: 24 bits DPI: connect MSB Ch B to D[32:39] */
|
|
val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT;
|
|
/* Syncmux bits zero: DPI channel A and B on output pins A and B resp */
|
|
writel(val, mcde->regs + MCDE_CONF0);
|
|
|
|
/* Clear any pending interrupts */
|
|
mcde_display_disable_irqs(mcde);
|
|
writel(0, mcde->regs + MCDE_IMSCERR);
|
|
writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
|
|
|
|
dev_info(drm->dev, "output in %s mode, format %dbpp\n",
|
|
(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ?
|
|
"VIDEO" : "CMD",
|
|
mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format));
|
|
formatter_cpp =
|
|
mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8;
|
|
dev_info(drm->dev, "overlay CPP %d bytes, DSI CPP %d bytes\n",
|
|
cpp,
|
|
formatter_cpp);
|
|
|
|
/* Calculations from mcde_fmtr_dsi.c, fmtr_dsi_enable_video() */
|
|
|
|
/*
|
|
* Set up FIFO A watermark level:
|
|
* 128 for LCD 32bpp video mode
|
|
* 48 for LCD 32bpp command mode
|
|
* 128 for LCD 16bpp video mode
|
|
* 64 for LCD 16bpp command mode
|
|
* 128 for HDMI 32bpp
|
|
* 192 for HDMI 16bpp
|
|
*/
|
|
fifo_wtrmrk = mode->hdisplay;
|
|
if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
|
|
fifo_wtrmrk = min(fifo_wtrmrk, 128);
|
|
pkt_div = 1;
|
|
} else {
|
|
fifo_wtrmrk = min(fifo_wtrmrk, 48);
|
|
/* The FIFO is 640 entries deep on this v3 hardware */
|
|
pkt_div = mcde_dsi_get_pkt_div(mode->hdisplay, 640);
|
|
}
|
|
dev_dbg(drm->dev, "FIFO watermark after flooring: %d bytes\n",
|
|
fifo_wtrmrk);
|
|
dev_dbg(drm->dev, "Packet divisor: %d bytes\n", pkt_div);
|
|
|
|
/* NOTE: pkt_div is 1 for video mode */
|
|
pkt_size = (formatter_ppl * formatter_cpp) / pkt_div;
|
|
/* Commands CMD8 need one extra byte */
|
|
if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO))
|
|
pkt_size++;
|
|
|
|
dev_dbg(drm->dev, "DSI packet size: %d * %d bytes per line\n",
|
|
pkt_size, pkt_div);
|
|
dev_dbg(drm->dev, "Overlay frame size: %u bytes\n",
|
|
mode->hdisplay * mode->vdisplay * cpp);
|
|
mcde->stride = mode->hdisplay * cpp;
|
|
dev_dbg(drm->dev, "Overlay line stride: %u bytes\n",
|
|
mcde->stride);
|
|
/* NOTE: pkt_div is 1 for video mode */
|
|
formatter_frame = pkt_size * pkt_div * formatter_lpf;
|
|
dev_dbg(drm->dev, "Formatter frame size: %u bytes\n", formatter_frame);
|
|
|
|
/* Drain the FIFO A + channel 0 pipe so we have a clean slate */
|
|
mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0);
|
|
|
|
/*
|
|
* We set up our display pipeline:
|
|
* EXTSRC 0 -> OVERLAY 0 -> CHANNEL 0 -> FIFO A -> DSI FORMATTER 0
|
|
*
|
|
* First configure the external source (memory) on external source 0
|
|
* using the desired bitstream/bitmap format
|
|
*/
|
|
mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format);
|
|
|
|
/*
|
|
* Configure overlay 0 according to format and mode and take input
|
|
* from external source 0 and route the output of this overlay to
|
|
* channel 0
|
|
*/
|
|
mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0,
|
|
MCDE_CHANNEL_0, mode, format, cpp);
|
|
|
|
/*
|
|
* Configure pixel-per-line and line-per-frame for channel 0 and then
|
|
* route channel 0 to FIFO A
|
|
*/
|
|
mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode);
|
|
|
|
/* Configure FIFO A to use DSI formatter 0 */
|
|
mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0,
|
|
fifo_wtrmrk);
|
|
|
|
/*
|
|
* This brings up the DSI bridge which is tightly connected
|
|
* to the MCDE DSI formatter.
|
|
*
|
|
* FIXME: if we want to use another formatter, such as DPI,
|
|
* we need to be more elaborate here and select the appropriate
|
|
* bridge.
|
|
*/
|
|
mcde_dsi_enable(mcde->bridge);
|
|
|
|
/* Configure the DSI formatter 0 for the DSI panel output */
|
|
mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0,
|
|
formatter_frame, pkt_size);
|
|
|
|
switch (mcde->flow_mode) {
|
|
case MCDE_COMMAND_TE_FLOW:
|
|
case MCDE_COMMAND_BTA_TE_FLOW:
|
|
case MCDE_VIDEO_TE_FLOW:
|
|
/* We are using TE in some comination */
|
|
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
|
val = MCDE_VSCRC_VSPOL;
|
|
else
|
|
val = 0;
|
|
writel(val, mcde->regs + MCDE_VSCRC0);
|
|
/* Enable VSYNC capture on TE0 */
|
|
val = readl(mcde->regs + MCDE_CRC);
|
|
val |= MCDE_CRC_SYCEN0;
|
|
writel(val, mcde->regs + MCDE_CRC);
|
|
break;
|
|
default:
|
|
/* No TE capture */
|
|
break;
|
|
}
|
|
|
|
drm_crtc_vblank_on(crtc);
|
|
|
|
/*
|
|
* If we're using oneshot mode we don't start the flow
|
|
* until each time the display is given an update, and
|
|
* then we disable it immediately after. For all other
|
|
* modes (command or video) we start the FIFO flow
|
|
* right here. This is necessary for the hardware to
|
|
* behave right.
|
|
*/
|
|
if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) {
|
|
mcde_enable_fifo(mcde, MCDE_FIFO_A);
|
|
dev_dbg(mcde->dev, "started MCDE video FIFO flow\n");
|
|
}
|
|
|
|
/* Enable MCDE with automatic clock gating */
|
|
val = readl(mcde->regs + MCDE_CR);
|
|
val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN;
|
|
writel(val, mcde->regs + MCDE_CR);
|
|
|
|
dev_info(drm->dev, "MCDE display is enabled\n");
|
|
}
|
|
|
|
static void mcde_display_disable(struct drm_simple_display_pipe *pipe)
|
|
{
|
|
struct drm_crtc *crtc = &pipe->crtc;
|
|
struct drm_device *drm = crtc->dev;
|
|
struct mcde *mcde = to_mcde(drm);
|
|
struct drm_pending_vblank_event *event;
|
|
int ret;
|
|
|
|
drm_crtc_vblank_off(crtc);
|
|
|
|
/* Disable FIFO A flow */
|
|
mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
|
|
|
|
/* This disables the DSI bridge */
|
|
mcde_dsi_disable(mcde->bridge);
|
|
|
|
event = crtc->state->event;
|
|
if (event) {
|
|
crtc->state->event = NULL;
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
drm_crtc_send_vblank_event(crtc, event);
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
}
|
|
|
|
ret = regulator_disable(mcde->epod);
|
|
if (ret)
|
|
dev_err(drm->dev, "can't disable EPOD regulator\n");
|
|
/* Make sure we are powered down (before we may power up again) */
|
|
usleep_range(50000, 70000);
|
|
|
|
dev_info(drm->dev, "MCDE display is disabled\n");
|
|
}
|
|
|
|
static void mcde_start_flow(struct mcde *mcde)
|
|
{
|
|
/* Request a TE ACK only in TE+BTA mode */
|
|
if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW)
|
|
mcde_dsi_te_request(mcde->mdsi);
|
|
|
|
/* Enable FIFO A flow */
|
|
mcde_enable_fifo(mcde, MCDE_FIFO_A);
|
|
|
|
/*
|
|
* If oneshot mode is enabled, the flow will be disabled
|
|
* when the TE0 IRQ arrives in the interrupt handler. Otherwise
|
|
* updates are continuously streamed to the display after this
|
|
* point.
|
|
*/
|
|
|
|
if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
|
|
/* Trigger a software sync out on channel 0 */
|
|
writel(MCDE_CHNLXSYNCHSW_SW_TRIG,
|
|
mcde->regs + MCDE_CHNL0SYNCHSW);
|
|
|
|
/*
|
|
* Disable FIFO A flow again: since we are using TE sync we
|
|
* need to wait for the FIFO to drain before we continue
|
|
* so repeated calls to this function will not cause a mess
|
|
* in the hardware by pushing updates will updates are going
|
|
* on already.
|
|
*/
|
|
mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
|
|
}
|
|
|
|
dev_dbg(mcde->dev, "started MCDE FIFO flow\n");
|
|
}
|
|
|
|
static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address)
|
|
{
|
|
/* Write bitmap base address to register */
|
|
writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);
|
|
/*
|
|
* Base address for next line this is probably only used
|
|
* in interlace modes.
|
|
*/
|
|
writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);
|
|
}
|
|
|
|
static void mcde_display_update(struct drm_simple_display_pipe *pipe,
|
|
struct drm_plane_state *old_pstate)
|
|
{
|
|
struct drm_crtc *crtc = &pipe->crtc;
|
|
struct drm_device *drm = crtc->dev;
|
|
struct mcde *mcde = to_mcde(drm);
|
|
struct drm_pending_vblank_event *event = crtc->state->event;
|
|
struct drm_plane *plane = &pipe->plane;
|
|
struct drm_plane_state *pstate = plane->state;
|
|
struct drm_framebuffer *fb = pstate->fb;
|
|
|
|
/*
|
|
* Handle any pending event first, we need to arm the vblank
|
|
* interrupt before sending any update to the display so we don't
|
|
* miss the interrupt.
|
|
*/
|
|
if (event) {
|
|
crtc->state->event = NULL;
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
/*
|
|
* Hardware must be on before we can arm any vblank event,
|
|
* this is not a scanout controller where there is always
|
|
* some periodic update going on, it is completely frozen
|
|
* until we get an update. If MCDE output isn't yet enabled,
|
|
* we just send a vblank dummy event back.
|
|
*/
|
|
if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) {
|
|
dev_dbg(mcde->dev, "arm vblank event\n");
|
|
drm_crtc_arm_vblank_event(crtc, event);
|
|
} else {
|
|
dev_dbg(mcde->dev, "insert fake vblank event\n");
|
|
drm_crtc_send_vblank_event(crtc, event);
|
|
}
|
|
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
}
|
|
|
|
/*
|
|
* We do not start sending framebuffer updates before the
|
|
* display is enabled. Update events will however be dispatched
|
|
* from the DRM core before the display is enabled.
|
|
*/
|
|
if (fb) {
|
|
mcde_set_extsrc(mcde, drm_fb_cma_get_gem_addr(fb, pstate, 0));
|
|
dev_info_once(mcde->dev, "first update of display contents\n");
|
|
/*
|
|
* Usually the flow is already active, unless we are in
|
|
* oneshot mode, then we need to kick the flow right here.
|
|
*/
|
|
if (mcde->flow_active == 0)
|
|
mcde_start_flow(mcde);
|
|
} else {
|
|
/*
|
|
* If an update is receieved before the MCDE is enabled
|
|
* (before mcde_display_enable() is called) we can't really
|
|
* do much with that buffer.
|
|
*/
|
|
dev_info(mcde->dev, "ignored a display update\n");
|
|
}
|
|
}
|
|
|
|
static int mcde_display_enable_vblank(struct drm_simple_display_pipe *pipe)
|
|
{
|
|
struct drm_crtc *crtc = &pipe->crtc;
|
|
struct drm_device *drm = crtc->dev;
|
|
struct mcde *mcde = to_mcde(drm);
|
|
u32 val;
|
|
|
|
/* Enable all VBLANK IRQs */
|
|
val = MCDE_PP_VCMPA |
|
|
MCDE_PP_VCMPB |
|
|
MCDE_PP_VSCC0 |
|
|
MCDE_PP_VSCC1 |
|
|
MCDE_PP_VCMPC0 |
|
|
MCDE_PP_VCMPC1;
|
|
writel(val, mcde->regs + MCDE_IMSCPP);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mcde_display_disable_vblank(struct drm_simple_display_pipe *pipe)
|
|
{
|
|
struct drm_crtc *crtc = &pipe->crtc;
|
|
struct drm_device *drm = crtc->dev;
|
|
struct mcde *mcde = to_mcde(drm);
|
|
|
|
/* Disable all VBLANK IRQs */
|
|
writel(0, mcde->regs + MCDE_IMSCPP);
|
|
/* Clear any pending IRQs */
|
|
writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
|
|
}
|
|
|
|
static struct drm_simple_display_pipe_funcs mcde_display_funcs = {
|
|
.check = mcde_display_check,
|
|
.enable = mcde_display_enable,
|
|
.disable = mcde_display_disable,
|
|
.update = mcde_display_update,
|
|
.enable_vblank = mcde_display_enable_vblank,
|
|
.disable_vblank = mcde_display_disable_vblank,
|
|
.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
|
|
};
|
|
|
|
int mcde_display_init(struct drm_device *drm)
|
|
{
|
|
struct mcde *mcde = to_mcde(drm);
|
|
int ret;
|
|
static const u32 formats[] = {
|
|
DRM_FORMAT_ARGB8888,
|
|
DRM_FORMAT_ABGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_RGB888,
|
|
DRM_FORMAT_BGR888,
|
|
DRM_FORMAT_ARGB4444,
|
|
DRM_FORMAT_ABGR4444,
|
|
DRM_FORMAT_XRGB4444,
|
|
DRM_FORMAT_XBGR4444,
|
|
/* These are actually IRGB1555 so intensity bit is lost */
|
|
DRM_FORMAT_XRGB1555,
|
|
DRM_FORMAT_XBGR1555,
|
|
DRM_FORMAT_RGB565,
|
|
DRM_FORMAT_BGR565,
|
|
DRM_FORMAT_YUV422,
|
|
};
|
|
|
|
ret = drm_simple_display_pipe_init(drm, &mcde->pipe,
|
|
&mcde_display_funcs,
|
|
formats, ARRAY_SIZE(formats),
|
|
NULL,
|
|
mcde->connector);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mcde_display_init);
|