![Julien Masson](/assets/img/avatar_default.png)
This patch introduce new enum which contains all VPU family (GXBB, GXL, GXM and G12A). This enum is used to detect the VPU compatible with the device. We only need to set .data to the corresponding enum in the device table, no need to check .compatible string anymore. Signed-off-by: Julien Masson <jmasson@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/87imqpz21w.fsf@masson.i-did-not-set--mail-host-address--so-tickle-me
164 lines
5.4 KiB
C
164 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*/
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#include <linux/export.h>
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#include "meson_drv.h"
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#include "meson_registers.h"
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#include "meson_vpp.h"
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/**
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* DOC: Video Post Processing
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*
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* VPP Handles all the Post Processing after the Scanout from the VIU
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* We handle the following post processings :
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*
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* - Postblend, Blends the OSD1 only
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* We exclude OSD2, VS1, VS1 and Preblend output
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* - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
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* use it only for interlace scanout
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* - Intermediate FIFO with default Amlogic values
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*
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* What is missing :
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*
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* - Preblend for video overlay pre-scaling
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* - OSD2 support for cursor framebuffer
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* - Video pre-scaling before postblend
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* - Full Vertical/Horizontal OSD scaling to support TV overscan
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* - HDR conversion
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*/
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void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
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{
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writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
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}
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static unsigned int vpp_filter_coefs_4point_bspline[] = {
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0x15561500, 0x14561600, 0x13561700, 0x12561800,
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0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
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0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
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0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
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0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
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0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
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0x05473301, 0x05463401, 0x04453601, 0x04433702,
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0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
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0x033d3d03
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};
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static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
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const unsigned int *coefs,
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bool is_horizontal)
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{
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int i;
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writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
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priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
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for (i = 0; i < 33; i++)
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writel_relaxed(coefs[i],
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priv->io_base + _REG(VPP_OSD_SCALE_COEF));
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}
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static const uint32_t vpp_filter_coefs_bicubic[] = {
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0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
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0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
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0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
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0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
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0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
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0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
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0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
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0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
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0xf84848f8
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};
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static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
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const unsigned int *coefs,
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bool is_horizontal)
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{
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int i;
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writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
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priv->io_base + _REG(VPP_SCALE_COEF_IDX));
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for (i = 0; i < 33; i++)
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writel_relaxed(coefs[i],
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priv->io_base + _REG(VPP_SCALE_COEF));
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}
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void meson_vpp_init(struct meson_drm *priv)
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{
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/* set dummy data default YUV black */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
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writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
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else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
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writel_bits_relaxed(0xff << 16, 0xff << 16,
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priv->io_base + _REG(VIU_MISC_CTRL1));
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writel_relaxed(VPP_PPS_DUMMY_DATA_MODE,
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priv->io_base + _REG(VPP_DOLBY_CTRL));
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writel_relaxed(0x1020080,
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priv->io_base + _REG(VPP_DUMMY_DATA1));
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} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
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writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
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/* Initialize vpu fifo control registers */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
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writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
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priv->io_base + _REG(VPP_OFIFO_SIZE));
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else
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writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f,
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priv->io_base + _REG(VPP_OFIFO_SIZE));
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writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
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priv->io_base + _REG(VPP_HOLD_LINES));
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if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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/* Turn off preblend */
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writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
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priv->io_base + _REG(VPP_MISC));
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/* Turn off POSTBLEND */
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
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priv->io_base + _REG(VPP_MISC));
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/* Force all planes off */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
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VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
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VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
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priv->io_base + _REG(VPP_MISC));
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/* Setup default VD settings */
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writel_relaxed(4096,
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priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
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writel_relaxed(4096,
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priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
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}
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/* Disable Scalers */
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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/* Set horizontal/vertical bank length and enable video scale out */
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writel_relaxed(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) |
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VPP_SC_VD_EN_ENABLE,
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priv->io_base + _REG(VPP_SC_MISC));
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/* Enable minus black level for vadj1 */
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writel_relaxed(VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,
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priv->io_base + _REG(VPP_VADJ_CTRL));
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/* Write in the proper filter coefficients. */
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meson_vpp_write_scaling_filter_coefs(priv,
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vpp_filter_coefs_4point_bspline, false);
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meson_vpp_write_scaling_filter_coefs(priv,
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vpp_filter_coefs_4point_bspline, true);
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/* Write the VD proper filter coefficients. */
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meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
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false);
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meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
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true);
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}
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