5c9b969f69
There are two PATBASE address registers, one for linear layout and other for tiled. The driver's address registers list misses the tiled PATBASE register. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
27 lines
653 B
C
27 lines
653 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 NVIDIA Corporation
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*/
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#ifndef TEGRA_GR2D_H
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#define TEGRA_GR2D_H
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#define GR2D_UA_BASE_ADDR 0x1a
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#define GR2D_VA_BASE_ADDR 0x1b
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#define GR2D_PAT_BASE_ADDR 0x26
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#define GR2D_DSTA_BASE_ADDR 0x2b
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#define GR2D_DSTB_BASE_ADDR 0x2c
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#define GR2D_DSTC_BASE_ADDR 0x2d
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#define GR2D_SRCA_BASE_ADDR 0x31
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#define GR2D_SRCB_BASE_ADDR 0x32
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#define GR2D_PATBASE_ADDR 0x47
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#define GR2D_SRC_BASE_ADDR_SB 0x48
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#define GR2D_DSTA_BASE_ADDR_SB 0x49
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#define GR2D_DSTB_BASE_ADDR_SB 0x4a
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#define GR2D_UA_BASE_ADDR_SB 0x4b
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#define GR2D_VA_BASE_ADDR_SB 0x4c
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#define GR2D_NUM_REGS 0x4d
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#endif
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