![Maxime Ripard](/assets/img/avatar_default.png)
The CRTC in vc4 is backed by two devices, the HVS that does the composition and the PixelValve that does the timing generation. The writeback is kind of a special case since it doesn't have an associated pixelvalve but goes straight from the HVS to the TXP. Therefore, it makes sense to move out the HVS setup code into helpers so that we can also reuse them from the TXP driver. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/96443394e81429ee38f070cfe231701b07e56d69.1591882579.git-series.maxime@cerno.tech
647 lines
19 KiB
C
647 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Broadcom
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*/
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/**
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* DOC: VC4 HVS module.
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*
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* The Hardware Video Scaler (HVS) is the piece of hardware that does
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* translation, scaling, colorspace conversion, and compositing of
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* pixels stored in framebuffers into a FIFO of pixels going out to
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* the Pixel Valve (CRTC). It operates at the system clock rate (the
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* system audio clock gate, specifically), which is much higher than
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* the pixel clock rate.
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*
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* There is a single global HVS, with multiple output FIFOs that can
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* be consumed by the PVs. This file just manages the resources for
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* the HVS, while the vc4_crtc.c code actually drives HVS setup for
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* each CRTC.
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*/
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#include <linux/component.h>
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#include <linux/platform_device.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_vblank.h>
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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static const struct debugfs_reg32 hvs_regs[] = {
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VC4_REG32(SCALER_DISPCTRL),
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VC4_REG32(SCALER_DISPSTAT),
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VC4_REG32(SCALER_DISPID),
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VC4_REG32(SCALER_DISPECTRL),
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VC4_REG32(SCALER_DISPPROF),
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VC4_REG32(SCALER_DISPDITHER),
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VC4_REG32(SCALER_DISPEOLN),
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VC4_REG32(SCALER_DISPLIST0),
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VC4_REG32(SCALER_DISPLIST1),
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VC4_REG32(SCALER_DISPLIST2),
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VC4_REG32(SCALER_DISPLSTAT),
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VC4_REG32(SCALER_DISPLACT0),
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VC4_REG32(SCALER_DISPLACT1),
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VC4_REG32(SCALER_DISPLACT2),
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VC4_REG32(SCALER_DISPCTRL0),
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VC4_REG32(SCALER_DISPBKGND0),
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VC4_REG32(SCALER_DISPSTAT0),
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VC4_REG32(SCALER_DISPBASE0),
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VC4_REG32(SCALER_DISPCTRL1),
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VC4_REG32(SCALER_DISPBKGND1),
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VC4_REG32(SCALER_DISPSTAT1),
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VC4_REG32(SCALER_DISPBASE1),
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VC4_REG32(SCALER_DISPCTRL2),
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VC4_REG32(SCALER_DISPBKGND2),
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VC4_REG32(SCALER_DISPSTAT2),
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VC4_REG32(SCALER_DISPBASE2),
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VC4_REG32(SCALER_DISPALPHA2),
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VC4_REG32(SCALER_OLEDOFFS),
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VC4_REG32(SCALER_OLEDCOEF0),
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VC4_REG32(SCALER_OLEDCOEF1),
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VC4_REG32(SCALER_OLEDCOEF2),
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};
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void vc4_hvs_dump_state(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
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int i;
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drm_print_regset32(&p, &vc4->hvs->regset);
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DRM_INFO("HVS ctx:\n");
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for (i = 0; i < 64; i += 4) {
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DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
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readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
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readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
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readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
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readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
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}
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}
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static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = m->private;
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struct drm_device *dev = node->minor->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_printer p = drm_seq_file_printer(m);
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drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
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return 0;
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}
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/* The filter kernel is composed of dwords each containing 3 9-bit
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* signed integers packed next to each other.
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*/
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#define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
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#define VC4_PPF_FILTER_WORD(c0, c1, c2) \
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((((c0) & 0x1ff) << 0) | \
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(((c1) & 0x1ff) << 9) | \
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(((c2) & 0x1ff) << 18))
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/* The whole filter kernel is arranged as the coefficients 0-16 going
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* up, then a pad, then 17-31 going down and reversed within the
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* dwords. This means that a linear phase kernel (where it's
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* symmetrical at the boundary between 15 and 16) has the last 5
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* dwords matching the first 5, but reversed.
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*/
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#define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
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c9, c10, c11, c12, c13, c14, c15) \
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{VC4_PPF_FILTER_WORD(c0, c1, c2), \
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VC4_PPF_FILTER_WORD(c3, c4, c5), \
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VC4_PPF_FILTER_WORD(c6, c7, c8), \
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VC4_PPF_FILTER_WORD(c9, c10, c11), \
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VC4_PPF_FILTER_WORD(c12, c13, c14), \
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VC4_PPF_FILTER_WORD(c15, c15, 0)}
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#define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
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#define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
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/* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
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* http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
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*/
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static const u32 mitchell_netravali_1_3_1_3_kernel[] =
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VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
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50, 82, 119, 155, 187, 213, 227);
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static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
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struct drm_mm_node *space,
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const u32 *kernel)
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{
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int ret, i;
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u32 __iomem *dst_kernel;
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ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
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if (ret) {
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DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
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ret);
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return ret;
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}
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dst_kernel = hvs->dlist + space->start;
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for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
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if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
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writel(kernel[i], &dst_kernel[i]);
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else {
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writel(kernel[VC4_KERNEL_DWORDS - i - 1],
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&dst_kernel[i]);
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}
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}
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return 0;
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}
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static void vc4_hvs_lut_load(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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u32 i;
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/* The LUT memory is laid out with each HVS channel in order,
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* each of which takes 256 writes for R, 256 for G, then 256
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* for B.
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*/
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HVS_WRITE(SCALER_GAMADDR,
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SCALER_GAMADDR_AUTOINC |
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(vc4_crtc->channel * 3 * crtc->gamma_size));
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for (i = 0; i < crtc->gamma_size; i++)
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HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
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for (i = 0; i < crtc->gamma_size; i++)
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HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
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for (i = 0; i < crtc->gamma_size; i++)
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HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
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}
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static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
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{
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_color_lut *lut = crtc->state->gamma_lut->data;
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u32 length = drm_color_lut_size(crtc->state->gamma_lut);
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u32 i;
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for (i = 0; i < length; i++) {
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vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
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vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
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vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
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}
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vc4_hvs_lut_load(crtc);
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}
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int vc4_hvs_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_plane *plane;
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unsigned long flags;
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const struct drm_plane_state *plane_state;
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u32 dlist_count = 0;
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int ret;
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/* The pixelvalve can only feed one encoder (and encoders are
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* 1:1 with connectors.)
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*/
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if (hweight32(state->connector_mask) > 1)
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return -EINVAL;
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drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
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dlist_count += vc4_plane_dlist_size(plane_state);
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dlist_count++; /* Account for SCALER_CTL0_END. */
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spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
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ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
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dlist_count);
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spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
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if (ret)
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return ret;
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return 0;
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}
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static void vc4_hvs_update_dlist(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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if (crtc->state->event) {
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unsigned long flags;
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crtc->state->event->pipe = drm_crtc_index(crtc);
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&dev->event_lock, flags);
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if (!vc4_state->feed_txp || vc4_state->txp_armed) {
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vc4_crtc->event = crtc->state->event;
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crtc->state->event = NULL;
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}
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HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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vc4_state->mm.start);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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} else {
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HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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vc4_state->mm.start);
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}
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}
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void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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bool oneshot = vc4_state->feed_txp;
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u32 dispctrl;
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vc4_hvs_update_dlist(crtc);
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/* Turn on the scaler, which will wait for vstart to start
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* compositing.
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* When feeding the transposer, we should operate in oneshot
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* mode.
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*/
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dispctrl = SCALER_DISPCTRLX_ENABLE;
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dispctrl |= VC4_SET_FIELD(mode->hdisplay,
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SCALER_DISPCTRLX_WIDTH) |
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VC4_SET_FIELD(mode->vdisplay,
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SCALER_DISPCTRLX_HEIGHT) |
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(oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
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HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
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}
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void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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u32 chan = vc4_crtc->channel;
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if (HVS_READ(SCALER_DISPCTRLX(chan)) &
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SCALER_DISPCTRLX_ENABLE) {
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HVS_WRITE(SCALER_DISPCTRLX(chan),
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SCALER_DISPCTRLX_RESET);
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/* While the docs say that reset is self-clearing, it
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* seems it doesn't actually.
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*/
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HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
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}
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/* Once we leave, the scaler should be disabled and its fifo empty. */
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WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
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WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
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SCALER_DISPSTATX_MODE) !=
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SCALER_DISPSTATX_MODE_DISABLED);
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WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
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(SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
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SCALER_DISPSTATX_EMPTY);
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}
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void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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struct drm_plane *plane;
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struct vc4_plane_state *vc4_plane_state;
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bool debug_dump_regs = false;
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bool enable_bg_fill = false;
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u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
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u32 __iomem *dlist_next = dlist_start;
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
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vc4_hvs_dump_state(dev);
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}
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/* Copy all the active planes' dlist contents to the hardware dlist. */
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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/* Is this the first active plane? */
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if (dlist_next == dlist_start) {
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/* We need to enable background fill when a plane
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* could be alpha blending from the background, i.e.
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* where no other plane is underneath. It suffices to
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* consider the first active plane here since we set
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* needs_bg_fill such that either the first plane
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* already needs it or all planes on top blend from
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* the first or a lower plane.
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*/
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vc4_plane_state = to_vc4_plane_state(plane->state);
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enable_bg_fill = vc4_plane_state->needs_bg_fill;
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}
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dlist_next += vc4_plane_write_dlist(plane, dlist_next);
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}
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writel(SCALER_CTL0_END, dlist_next);
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dlist_next++;
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WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
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if (enable_bg_fill)
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/* This sets a black background color fill, as is the case
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* with other DRM drivers.
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*/
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HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
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HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
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SCALER_DISPBKGND_FILL);
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/* Only update DISPLIST if the CRTC was already running and is not
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* being disabled.
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* vc4_crtc_enable() takes care of updating the dlist just after
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* re-enabling VBLANK interrupts and before enabling the engine.
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* If the CRTC is being disabled, there's no point in updating this
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* information.
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*/
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if (crtc->state->active && old_state->active)
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vc4_hvs_update_dlist(crtc);
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if (crtc->state->color_mgmt_changed) {
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u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
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if (crtc->state->gamma_lut) {
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vc4_hvs_update_gamma_lut(crtc);
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dispbkgndx |= SCALER_DISPBKGND_GAMMA;
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} else {
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/* Unsetting DISPBKGND_GAMMA skips the gamma lut step
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* in hardware, which is the same as a linear lut that
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* DRM expects us to use in absence of a user lut.
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*/
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dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
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}
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HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
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}
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
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vc4_hvs_dump_state(dev);
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}
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}
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void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
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if (vc4_crtc->data->hvs_channel == 2) {
|
|
u32 dispctrl;
|
|
u32 dsp3_mux;
|
|
|
|
/*
|
|
* SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
|
|
* FIFO X'.
|
|
* SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
|
|
*
|
|
* DSP3 is connected to FIFO2 unless the transposer is
|
|
* enabled. In this case, FIFO 2 is directly accessed by the
|
|
* TXP IP, and we need to disable the FIFO2 -> pixelvalve1
|
|
* route.
|
|
*/
|
|
if (vc4_state->feed_txp)
|
|
dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
|
|
else
|
|
dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
|
|
|
|
dispctrl = HVS_READ(SCALER_DISPCTRL) &
|
|
~SCALER_DISPCTRL_DSP3_MUX_MASK;
|
|
HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
|
|
}
|
|
|
|
HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
|
|
SCALER_DISPBKGND_AUTOHS |
|
|
SCALER_DISPBKGND_GAMMA |
|
|
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
|
|
|
|
/* Reload the LUT, since the SRAMs would have been disabled if
|
|
* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
|
|
*/
|
|
vc4_hvs_lut_load(crtc);
|
|
}
|
|
|
|
void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
|
|
|
|
dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
|
|
|
|
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
|
|
}
|
|
|
|
void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
|
|
|
|
dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
|
|
|
|
HVS_WRITE(SCALER_DISPSTAT,
|
|
SCALER_DISPSTAT_EUFLOW(channel));
|
|
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
|
|
}
|
|
|
|
static void vc4_hvs_report_underrun(struct drm_device *dev)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
atomic_inc(&vc4->underrun);
|
|
DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
|
|
}
|
|
|
|
static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
|
|
{
|
|
struct drm_device *dev = data;
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
irqreturn_t irqret = IRQ_NONE;
|
|
int channel;
|
|
u32 control;
|
|
u32 status;
|
|
|
|
status = HVS_READ(SCALER_DISPSTAT);
|
|
control = HVS_READ(SCALER_DISPCTRL);
|
|
|
|
for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
|
|
/* Interrupt masking is not always honored, so check it here. */
|
|
if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
|
|
control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
|
|
vc4_hvs_mask_underrun(dev, channel);
|
|
vc4_hvs_report_underrun(dev);
|
|
|
|
irqret = IRQ_HANDLED;
|
|
}
|
|
}
|
|
|
|
/* Clear every per-channel interrupt flag. */
|
|
HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
|
|
SCALER_DISPSTAT_IRQMASK(1) |
|
|
SCALER_DISPSTAT_IRQMASK(2));
|
|
|
|
return irqret;
|
|
}
|
|
|
|
static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct drm_device *drm = dev_get_drvdata(master);
|
|
struct vc4_dev *vc4 = drm->dev_private;
|
|
struct vc4_hvs *hvs = NULL;
|
|
int ret;
|
|
u32 dispctrl;
|
|
|
|
hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
|
|
if (!hvs)
|
|
return -ENOMEM;
|
|
|
|
hvs->pdev = pdev;
|
|
|
|
hvs->regs = vc4_ioremap_regs(pdev, 0);
|
|
if (IS_ERR(hvs->regs))
|
|
return PTR_ERR(hvs->regs);
|
|
|
|
hvs->regset.base = hvs->regs;
|
|
hvs->regset.regs = hvs_regs;
|
|
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
|
|
|
|
hvs->dlist = hvs->regs + SCALER_DLIST_START;
|
|
|
|
spin_lock_init(&hvs->mm_lock);
|
|
|
|
/* Set up the HVS display list memory manager. We never
|
|
* overwrite the setup from the bootloader (just 128b out of
|
|
* our 16K), since we don't want to scramble the screen when
|
|
* transitioning from the firmware's boot setup to runtime.
|
|
*/
|
|
drm_mm_init(&hvs->dlist_mm,
|
|
HVS_BOOTLOADER_DLIST_END,
|
|
(SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
|
|
|
|
/* Set up the HVS LBM memory manager. We could have some more
|
|
* complicated data structure that allowed reuse of LBM areas
|
|
* between planes when they don't overlap on the screen, but
|
|
* for now we just allocate globally.
|
|
*/
|
|
drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
|
|
|
|
/* Upload filter kernels. We only have the one for now, so we
|
|
* keep it around for the lifetime of the driver.
|
|
*/
|
|
ret = vc4_hvs_upload_linear_kernel(hvs,
|
|
&hvs->mitchell_netravali_filter,
|
|
mitchell_netravali_1_3_1_3_kernel);
|
|
if (ret)
|
|
return ret;
|
|
|
|
vc4->hvs = hvs;
|
|
|
|
dispctrl = HVS_READ(SCALER_DISPCTRL);
|
|
|
|
dispctrl |= SCALER_DISPCTRL_ENABLE;
|
|
dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
|
|
SCALER_DISPCTRL_DISPEIRQ(1) |
|
|
SCALER_DISPCTRL_DISPEIRQ(2);
|
|
|
|
/* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
|
|
* be unused.
|
|
*/
|
|
dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
|
|
dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
|
|
SCALER_DISPCTRL_SLVWREIRQ |
|
|
SCALER_DISPCTRL_SLVRDEIRQ |
|
|
SCALER_DISPCTRL_DSPEIEOF(0) |
|
|
SCALER_DISPCTRL_DSPEIEOF(1) |
|
|
SCALER_DISPCTRL_DSPEIEOF(2) |
|
|
SCALER_DISPCTRL_DSPEIEOLN(0) |
|
|
SCALER_DISPCTRL_DSPEIEOLN(1) |
|
|
SCALER_DISPCTRL_DSPEIEOLN(2) |
|
|
SCALER_DISPCTRL_DSPEISLUR(0) |
|
|
SCALER_DISPCTRL_DSPEISLUR(1) |
|
|
SCALER_DISPCTRL_DSPEISLUR(2) |
|
|
SCALER_DISPCTRL_SCLEIRQ);
|
|
dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
|
|
|
|
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
|
|
|
|
ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
|
|
vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
|
|
if (ret)
|
|
return ret;
|
|
|
|
vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
|
|
vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun,
|
|
NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void vc4_hvs_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct drm_device *drm = dev_get_drvdata(master);
|
|
struct vc4_dev *vc4 = drm->dev_private;
|
|
|
|
if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
|
|
drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
|
|
|
|
drm_mm_takedown(&vc4->hvs->dlist_mm);
|
|
drm_mm_takedown(&vc4->hvs->lbm_mm);
|
|
|
|
vc4->hvs = NULL;
|
|
}
|
|
|
|
static const struct component_ops vc4_hvs_ops = {
|
|
.bind = vc4_hvs_bind,
|
|
.unbind = vc4_hvs_unbind,
|
|
};
|
|
|
|
static int vc4_hvs_dev_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &vc4_hvs_ops);
|
|
}
|
|
|
|
static int vc4_hvs_dev_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &vc4_hvs_ops);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id vc4_hvs_dt_match[] = {
|
|
{ .compatible = "brcm,bcm2835-hvs" },
|
|
{}
|
|
};
|
|
|
|
struct platform_driver vc4_hvs_driver = {
|
|
.probe = vc4_hvs_dev_probe,
|
|
.remove = vc4_hvs_dev_remove,
|
|
.driver = {
|
|
.name = "vc4_hvs",
|
|
.of_match_table = vc4_hvs_dt_match,
|
|
},
|
|
};
|