71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright (C) 2017 NXP
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*/
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#ifndef _MC_CGM_H
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#define _MC_CGM_H
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#define ARMPLL_PLLDIG(mc_cgm) (mc_cgm)
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#define ARMPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x40)
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#define ARMPLL_PLLDIG_PLLDV_MFD (50)
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#define ARMPLL_PLLDIG_PLLDV_MFN (0)
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#define ARMPLL_PLLDIG_PLLDV_RFDPHI0 (1)
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#define ARMPLL_PLLDIG_PLLDV_RFDPHI1 (1)
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#define ARMPLL_PLLDIG_DFS0_MFN (195)
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#define ARMPLL_PLLDIG_DFS1_MFN (171)
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#define ARMPLL_PLLDIG_DFS2_MFN (171)
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#define PERIPHPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x80)
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#define PERIPHPLL_PLLDIG_PLLDV_MFD (30)
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#define PERIPHPLL_PLLDIG_PLLDV_MFN (0)
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#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI0 (0x1)
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#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI1 (0x1)
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#define ENETPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x100)
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#define ENETPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x100 + 0x40)
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#define ENETPLL_PLLDIG_PLLDV_MFD (50)
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#define ENETPLL_PLLDIG_PLLDV_MFN (0)
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#define ENETPLL_PLLDIG_PLLDV_RFDPHI0 (0x1)
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#define ENETPLL_PLLDIG_PLLDV_RFDPHI1 (0x1)
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#define ENETPLL_PLLDIG_DFS0_MFN (220)
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#define ENETPLL_PLLDIG_DFS1_MFN (220)
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#define ENETPLL_PLLDIG_DFS2_MFN (33)
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#define ENETPLL_PLLDIG_DFS3_MFN (1)
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/* MC_CGM_SC_SS */
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#define CGM_SC_SS(mc_cgm) (((mc_cgm) + 0x7E4))
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/* MC_CGM_SC_DCn */
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#define CGM_SC_DCn(mc_cgm, dc) (((mc_cgm) + 0x7E8) + ((dc) * 0x4))
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#define MC_CGM_SC_DCn_PREDIV_OFFSET (16)
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#define MC_CGM_SC_DCn_PREDIV_SIZE (3)
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#define MC_CGM_SC_DCn_DE (1 << 31)
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#define MC_CGM_SC_SEL_OFFSET (24)
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#define MC_CGM_SC_SEL_SIZE (4)
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/* MC_CGM_ACn_DCm */
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#define CGM_ACn_DCm(mc_cgm, ac, dc) (((mc_cgm) + 0x808) + ((ac) * 0x20)\
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+ ((dc) * 0x4))
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#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & \
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((val) \
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<< MC_CGM_ACn_DCm_PREDIV_OFFSET))
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#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000)
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#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16)
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#define MC_CGM_ACn_DCm_PREDIV_SIZE (5)
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#define MC_CGM_ACn_DCm_DE (1 << 31)
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/* MC_CGM_ACn_SC/MC_CGM_ACn_SS */
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#define CGM_ACn_SC(mc_cgm, ac) (((mc_cgm) + 0x800) + ((ac) * 0x20))
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#define CGM_ACn_SS(mc_cgm, ac) (((mc_cgm) + 0x804) + ((ac) * 0x24))
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#define MC_CGM_ACn_SEL_MASK (0x07000000)
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#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & \
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(((source) & 0x7) \
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<< MC_CGM_ACn_SEL_OFFSET))
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#define MC_CGM_ACn_SEL_OFFSET (24)
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#define MC_CGM_ACn_SEL_SIZE (4)
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#endif
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