111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright (C) 2017 NXP
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*/
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#ifndef _MC_ME_H
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#define _MC_ME_H
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/* MC_ME registers definitions */
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/* MC_ME_GS */
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#define MC_ME_GS(mc_me) ((mc_me) + 0x00000000)
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/* MC_ME_MCTL */
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#define MC_ME_MCTL(mc_me) ((mc_me) + 0x00000004)
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#define MC_ME_MCTL_RESET (0x0 << 28)
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#define MC_ME_MCTL_TEST (0x1 << 28)
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#define MC_ME_MCTL_DRUN (0x3 << 28)
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#define MC_ME_MCTL_RUN0 (0x4 << 28)
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#define MC_ME_MCTL_RUN1 (0x5 << 28)
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#define MC_ME_MCTL_RUN2 (0x6 << 28)
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#define MC_ME_MCTL_RUN3 (0x7 << 28)
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#define MC_ME_GS_S_MTRANS (1 << 27)
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#define MC_ME_MCTL_KEY (0x00005AF0)
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#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F)
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/*
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* MC_ME_RESET_MC/MC_ME_TEST_MC
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* MC_ME_DRUN_MC
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* MC_ME_RUNn_MC
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*/
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#define MC_ME_RESET_MC(mc_me) ((mc_me) + 0x00000020)
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#define MC_ME_TEST_MC(mc_me) ((mc_me) + 0x00000024)
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#define MC_ME_DRUN_MC(mc_me) ((mc_me) + 0x0000002C)
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#define MC_ME_RUNn_MC(mc_me, n) ((mc_me) + 0x00000030 + 0x4 * (n))
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#define MC_ME_MODE_MC_SYSCLK_OFFSET (0)
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#define MC_ME_MODE_MC_SYSCLK_SIZE (0x3)
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#define MC_ME_MODE_MC_SYSCLK(val) (MC_ME_MODE_MC_SYSCLK_MASK & (val))
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#define MC_ME_MODE_MC_SYSCLK_MASK (0x0000000F)
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#define MC_ME_MODE_MC_FIRCON (1 << 4)
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#define MC_ME_MODE_MC_XOSCON (1 << 5)
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#define MC_ME_MODE_MC_ARMPLL (1 << 6)
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#define MC_ME_MODE_MC_PERIPHPLL (1 << 7)
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#define MC_ME_MODE_MC_ENETPLL (1 << 8)
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#define MC_ME_MODE_MC_DDRPLL (1 << 9)
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#define MC_ME_MODE_MC_VIDEOPLL (1 << 10)
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#define MC_ME_MODE_MC_MVRON (1 << 20)
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/* MC_ME_DRUN_SEC_CC_I */
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#define MC_ME_DRUN_SEC_CC_I(mc_me) ((mc_me) + 0x260)
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/* MC_ME_RUNn_SEC_CC_I */
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#define MC_ME_RUNn_SEC_CC_I(mc_me, n) ((mc_me) + 0x270 + (n) * 0x10)
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#define MC_ME_MODE_SEC_CC_I_SYSCLK1_OFFSET (4)
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#define MC_ME_MODE_SEC_CC_I_SYSCLK2_OFFSET (8)
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#define MC_ME_MODE_SEC_CC_I_SYSCLK3_OFFSET (12)
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/* Consider only the defined clocks */
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#define MC_ME_MODE_SEC_CC_I_SYSCLK1_SIZE (0x3)
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#define MC_ME_MODE_SEC_CC_I_SYSCLK2_SIZE (0x3)
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#define MC_ME_MODE_SEC_CC_I_SYSCLK3_SIZE (0x3)
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/* MC_ME_RUN_PCn */
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#define MC_ME_RUN_PCn(mc_me, n) (mc_me + 0x00000080 + 0x4 * (n))
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#define MC_ME_RUN_PCn_MAX_IDX (7)
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#define MC_ME_RUN_PCn_RESET (1 << 0)
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#define MC_ME_RUN_PCn_TEST (1 << 1)
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#define MC_ME_RUN_PCn_DRUN (1 << 3)
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#define MC_ME_RUN_PCn_RUN0 (1 << 4)
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#define MC_ME_RUN_PCn_RUN1 (1 << 5)
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#define MC_ME_RUN_PCn_RUN2 (1 << 6)
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#define MC_ME_RUN_PCn_RUN3 (1 << 7)
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#define MC_ME_PCTLn(mc_me, n) (mc_me + 0xC0 + 4 * (n >> 2) + \
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(3 - (n) % 4))
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static inline void entry_to_target_mode(void __iomem *mc_me, u32 mode)
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{
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writel_relaxed(mode | MC_ME_MCTL_KEY, MC_ME_MCTL(mc_me));
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writel_relaxed(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL(mc_me));
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while ((readl_relaxed(MC_ME_GS(mc_me)) &
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MC_ME_GS_S_MTRANS) != 0x00000000)
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;
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}
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static inline void enable_cpumodes_onperipheralconfig(void __iomem *mc_me,
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u32 modes, u32 run_pc_idx)
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{
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WARN_ON(run_pc_idx > MC_ME_RUN_PCn_MAX_IDX);
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if (run_pc_idx > MC_ME_RUN_PCn_MAX_IDX)
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return;
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writel_relaxed(modes, MC_ME_RUN_PCn(mc_me, run_pc_idx));
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}
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static inline void enable_clocks_sources(u32 flags, u32 clks,
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void __iomem *xrun_mc_addr)
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{
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writel_relaxed(readl_relaxed(xrun_mc_addr) | flags | clks,
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xrun_mc_addr);
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}
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static inline void enable_sysclock(u32 clk, void __iomem *xrun_mc_addr)
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{
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writel_relaxed(readl_relaxed(xrun_mc_addr) & clk,
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xrun_mc_addr);
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}
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#endif
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