![Chris Wilson](/assets/img/avatar_default.png)
As mentioned in the previous commit, reads and writes from both the CPU and GPU go through the LLC. This gives us coherency between the CPU and GPU irrespective of the attribute settings either device sets. We can use to avoid having to clflush even uncached memory. Except for the scanout. The scanout resides within another functional block that does not use the LLC but reads directly from main memory. So in order to maintain coherency with the scanout, writes to uncached memory must be flushed. In order to optimize writes elsewhere, we start tracking whether an framebuffer is attached to an object. v2: Use pin_display tracking rather than fb_count (to ensure we flush cursors as well etc) and only force the clflush along explicit writes to the scanout paths (i.e. pin_to_display_plane and pwrite into scanout). v3: Force the flush after hitting the slowpath in pwrite, as after dropping the lock the object's cache domain may be invalidated. (Ville) Based on a patch by Ville Syrjälä. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
935 lines
26 KiB
C
935 lines
26 KiB
C
/*
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* Copyright © 2010 Daniel Vetter
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#define GEN6_PPGTT_PD_ENTRIES 512
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#define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
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/* PPGTT stuff */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
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#define GEN6_PDE_VALID (1 << 0)
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/* gen6+ has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_VALID (1 << 0)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define HSW_PTE_UNCACHED (0)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
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/* Cacheability Control is a 4-bit value. The low three bits are stored in *
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* bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
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*/
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#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
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(((bits) & 0x8) << (11 - 3)))
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#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
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#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
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#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
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static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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{
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gen6_gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= GEN6_PTE_ADDR_ENCODE(addr);
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switch (level) {
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case I915_CACHE_L3_LLC:
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case I915_CACHE_LLC:
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pte |= GEN6_PTE_CACHE_LLC;
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break;
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case I915_CACHE_NONE:
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pte |= GEN6_PTE_UNCACHED;
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break;
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default:
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WARN_ON(1);
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}
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return pte;
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}
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static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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{
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gen6_gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= GEN6_PTE_ADDR_ENCODE(addr);
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switch (level) {
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case I915_CACHE_L3_LLC:
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pte |= GEN7_PTE_CACHE_L3_LLC;
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break;
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case I915_CACHE_LLC:
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pte |= GEN6_PTE_CACHE_LLC;
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break;
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case I915_CACHE_NONE:
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pte |= GEN6_PTE_UNCACHED;
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break;
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default:
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WARN_ON(1);
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}
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return pte;
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}
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#define BYT_PTE_WRITEABLE (1 << 1)
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#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
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static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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{
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gen6_gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= GEN6_PTE_ADDR_ENCODE(addr);
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/* Mark the page as writeable. Other platforms don't have a
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* setting for read-only/writable, so this matches that behavior.
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*/
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pte |= BYT_PTE_WRITEABLE;
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if (level != I915_CACHE_NONE)
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pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
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return pte;
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}
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static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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{
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gen6_gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= HSW_PTE_ADDR_ENCODE(addr);
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if (level != I915_CACHE_NONE)
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pte |= HSW_WB_LLC_AGE3;
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return pte;
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}
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static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
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enum i915_cache_level level)
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{
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gen6_gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= HSW_PTE_ADDR_ENCODE(addr);
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if (level != I915_CACHE_NONE)
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pte |= HSW_WB_ELLC_LLC_AGE0;
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return pte;
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}
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static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
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{
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struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
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gen6_gtt_pte_t __iomem *pd_addr;
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uint32_t pd_entry;
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int i;
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WARN_ON(ppgtt->pd_offset & 0x3f);
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pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
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ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = ppgtt->pt_dma_addr[i];
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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writel(pd_entry, pd_addr + i);
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}
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readl(pd_addr);
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}
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static int gen6_ppgtt_enable(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t pd_offset;
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struct intel_ring_buffer *ring;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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int i;
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BUG_ON(ppgtt->pd_offset & 0x3f);
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gen6_write_pdes(ppgtt);
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pd_offset = ppgtt->pd_offset;
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pd_offset /= 64; /* in cachelines, */
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pd_offset <<= 16;
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if (INTEL_INFO(dev)->gen == 6) {
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uint32_t ecochk, gab_ctl, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
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ECOBITS_PPGTT_CACHE64B);
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gab_ctl = I915_READ(GAB_CTL);
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I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
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ecochk = I915_READ(GAM_ECOCHK);
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I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
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ECOCHK_PPGTT_CACHE64B);
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I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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} else if (INTEL_INFO(dev)->gen >= 7) {
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uint32_t ecochk, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
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ecochk = I915_READ(GAM_ECOCHK);
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if (IS_HASWELL(dev)) {
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ecochk |= ECOCHK_PPGTT_WB_HSW;
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} else {
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ecochk |= ECOCHK_PPGTT_LLC_IVB;
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ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
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}
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I915_WRITE(GAM_ECOCHK, ecochk);
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/* GFX_MODE is per-ring on gen7+ */
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}
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for_each_ring(ring, dev_priv, i) {
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if (INTEL_INFO(dev)->gen >= 7)
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I915_WRITE(RING_MODE_GEN7(ring),
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_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
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I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
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}
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return 0;
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}
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/* PPGTT support for Sandybdrige/Gen6 and later */
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static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
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unsigned first_entry,
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unsigned num_entries)
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{
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struct i915_hw_ppgtt *ppgtt =
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container_of(vm, struct i915_hw_ppgtt, base);
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gen6_gtt_pte_t *pt_vaddr, scratch_pte;
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unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned last_pte, i;
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scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
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while (num_entries) {
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last_pte = first_pte + num_entries;
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if (last_pte > I915_PPGTT_PT_ENTRIES)
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last_pte = I915_PPGTT_PT_ENTRIES;
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
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for (i = first_pte; i < last_pte; i++)
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pt_vaddr[i] = scratch_pte;
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kunmap_atomic(pt_vaddr);
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num_entries -= last_pte - first_pte;
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first_pte = 0;
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act_pt++;
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}
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}
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static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
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struct sg_table *pages,
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unsigned first_entry,
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enum i915_cache_level cache_level)
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{
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struct i915_hw_ppgtt *ppgtt =
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container_of(vm, struct i915_hw_ppgtt, base);
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gen6_gtt_pte_t *pt_vaddr;
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unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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struct sg_page_iter sg_iter;
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
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for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
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dma_addr_t page_addr;
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page_addr = sg_page_iter_dma_address(&sg_iter);
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pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level);
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if (++act_pte == I915_PPGTT_PT_ENTRIES) {
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kunmap_atomic(pt_vaddr);
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act_pt++;
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
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act_pte = 0;
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}
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}
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kunmap_atomic(pt_vaddr);
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}
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static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
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{
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struct i915_hw_ppgtt *ppgtt =
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container_of(vm, struct i915_hw_ppgtt, base);
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int i;
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drm_mm_takedown(&ppgtt->base.mm);
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if (ppgtt->pt_dma_addr) {
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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pci_unmap_page(ppgtt->base.dev->pdev,
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ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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__free_page(ppgtt->pt_pages[i]);
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kfree(ppgtt->pt_pages);
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kfree(ppgtt);
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}
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static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
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{
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struct drm_device *dev = ppgtt->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned first_pd_entry_in_global_pt;
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int i;
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int ret = -ENOMEM;
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/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
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* entries. For aliasing ppgtt support we just steal them at the end for
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* now. */
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first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
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ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
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ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
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ppgtt->enable = gen6_ppgtt_enable;
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ppgtt->base.clear_range = gen6_ppgtt_clear_range;
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ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
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ppgtt->base.cleanup = gen6_ppgtt_cleanup;
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ppgtt->base.scratch = dev_priv->gtt.base.scratch;
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ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_pages)
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return -ENOMEM;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
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if (!ppgtt->pt_pages[i])
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goto err_pt_alloc;
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}
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ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_dma_addr)
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goto err_pt_alloc;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
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ret = -EIO;
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goto err_pd_pin;
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}
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ppgtt->pt_dma_addr[i] = pt_addr;
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}
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ppgtt->base.clear_range(&ppgtt->base, 0,
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ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES);
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ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
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return 0;
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err_pd_pin:
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if (ppgtt->pt_dma_addr) {
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for (i--; i >= 0; i--)
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pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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err_pt_alloc:
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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if (ppgtt->pt_pages[i])
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__free_page(ppgtt->pt_pages[i]);
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}
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kfree(ppgtt->pt_pages);
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return ret;
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}
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static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt;
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int ret;
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ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
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if (!ppgtt)
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return -ENOMEM;
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ppgtt->base.dev = dev;
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if (INTEL_INFO(dev)->gen < 8)
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ret = gen6_ppgtt_init(ppgtt);
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else
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BUG();
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if (ret)
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kfree(ppgtt);
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else {
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
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ppgtt->base.total);
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}
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return ret;
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}
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void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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if (!ppgtt)
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return;
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ppgtt->base.cleanup(&ppgtt->base);
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dev_priv->mm.aliasing_ppgtt = NULL;
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}
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void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
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i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
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cache_level);
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}
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void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj)
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{
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ppgtt->base.clear_range(&ppgtt->base,
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i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT);
|
|
}
|
|
|
|
extern int intel_iommu_gfx_mapped;
|
|
/* Certain Gen5 chipsets require require idling the GPU before
|
|
* unmapping anything from the GTT when VT-d is enabled.
|
|
*/
|
|
static inline bool needs_idle_maps(struct drm_device *dev)
|
|
{
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
/* Query intel_iommu to see if we need the workaround. Presumably that
|
|
* was loaded first.
|
|
*/
|
|
if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
|
|
return true;
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
static bool do_idling(struct drm_i915_private *dev_priv)
|
|
{
|
|
bool ret = dev_priv->mm.interruptible;
|
|
|
|
if (unlikely(dev_priv->gtt.do_idle_maps)) {
|
|
dev_priv->mm.interruptible = false;
|
|
if (i915_gpu_idle(dev_priv->dev)) {
|
|
DRM_ERROR("Couldn't idle GPU\n");
|
|
/* Wait a bit, in hopes it avoids the hang */
|
|
udelay(10);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
|
|
{
|
|
if (unlikely(dev_priv->gtt.do_idle_maps))
|
|
dev_priv->mm.interruptible = interruptible;
|
|
}
|
|
|
|
void i915_gem_restore_gtt_mappings(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
/* First fill our portion of the GTT with scratch pages */
|
|
dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
|
|
dev_priv->gtt.base.start / PAGE_SIZE,
|
|
dev_priv->gtt.base.total / PAGE_SIZE);
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
|
i915_gem_clflush_object(obj, obj->pin_display);
|
|
i915_gem_gtt_bind_object(obj, obj->cache_level);
|
|
}
|
|
|
|
i915_gem_chipset_flush(dev);
|
|
}
|
|
|
|
int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
|
|
{
|
|
if (obj->has_dma_mapping)
|
|
return 0;
|
|
|
|
if (!dma_map_sg(&obj->base.dev->pdev->dev,
|
|
obj->pages->sgl, obj->pages->nents,
|
|
PCI_DMA_BIDIRECTIONAL))
|
|
return -ENOSPC;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Binds an object into the global gtt with the specified cache level. The object
|
|
* will be accessible to the GPU via commands whose operands reference offsets
|
|
* within the global GTT as well as accessible by the GPU through the GMADR
|
|
* mapped BAR (dev_priv->mm.gtt->gtt).
|
|
*/
|
|
static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
|
|
struct sg_table *st,
|
|
unsigned int first_entry,
|
|
enum i915_cache_level level)
|
|
{
|
|
struct drm_i915_private *dev_priv = vm->dev->dev_private;
|
|
gen6_gtt_pte_t __iomem *gtt_entries =
|
|
(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
|
|
int i = 0;
|
|
struct sg_page_iter sg_iter;
|
|
dma_addr_t addr;
|
|
|
|
for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
|
|
addr = sg_page_iter_dma_address(&sg_iter);
|
|
iowrite32(vm->pte_encode(addr, level), >t_entries[i]);
|
|
i++;
|
|
}
|
|
|
|
/* XXX: This serves as a posting read to make sure that the PTE has
|
|
* actually been updated. There is some concern that even though
|
|
* registers and PTEs are within the same BAR that they are potentially
|
|
* of NUMA access patterns. Therefore, even with the way we assume
|
|
* hardware should work, we must keep this posting read for paranoia.
|
|
*/
|
|
if (i != 0)
|
|
WARN_ON(readl(>t_entries[i-1]) !=
|
|
vm->pte_encode(addr, level));
|
|
|
|
/* This next bit makes the above posting read even more important. We
|
|
* want to flush the TLBs only after we're certain all the PTE updates
|
|
* have finished.
|
|
*/
|
|
I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
|
|
POSTING_READ(GFX_FLSH_CNTL_GEN6);
|
|
}
|
|
|
|
static void gen6_ggtt_clear_range(struct i915_address_space *vm,
|
|
unsigned int first_entry,
|
|
unsigned int num_entries)
|
|
{
|
|
struct drm_i915_private *dev_priv = vm->dev->dev_private;
|
|
gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
|
|
(gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
|
|
const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
|
|
int i;
|
|
|
|
if (WARN(num_entries > max_entries,
|
|
"First entry = %d; Num entries = %d (max=%d)\n",
|
|
first_entry, num_entries, max_entries))
|
|
num_entries = max_entries;
|
|
|
|
scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
|
|
for (i = 0; i < num_entries; i++)
|
|
iowrite32(scratch_pte, >t_base[i]);
|
|
readl(gtt_base);
|
|
}
|
|
|
|
|
|
static void i915_ggtt_insert_entries(struct i915_address_space *vm,
|
|
struct sg_table *st,
|
|
unsigned int pg_start,
|
|
enum i915_cache_level cache_level)
|
|
{
|
|
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
|
|
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
|
|
|
|
intel_gtt_insert_sg_entries(st, pg_start, flags);
|
|
|
|
}
|
|
|
|
static void i915_ggtt_clear_range(struct i915_address_space *vm,
|
|
unsigned int first_entry,
|
|
unsigned int num_entries)
|
|
{
|
|
intel_gtt_clear_range(first_entry, num_entries);
|
|
}
|
|
|
|
|
|
void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
|
|
enum i915_cache_level cache_level)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
|
|
|
|
dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
|
|
entry,
|
|
cache_level);
|
|
|
|
obj->has_global_gtt_mapping = 1;
|
|
}
|
|
|
|
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
|
|
|
|
dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
|
|
entry,
|
|
obj->base.size >> PAGE_SHIFT);
|
|
|
|
obj->has_global_gtt_mapping = 0;
|
|
}
|
|
|
|
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
bool interruptible;
|
|
|
|
interruptible = do_idling(dev_priv);
|
|
|
|
if (!obj->has_dma_mapping)
|
|
dma_unmap_sg(&dev->pdev->dev,
|
|
obj->pages->sgl, obj->pages->nents,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
undo_idling(dev_priv, interruptible);
|
|
}
|
|
|
|
static void i915_gtt_color_adjust(struct drm_mm_node *node,
|
|
unsigned long color,
|
|
unsigned long *start,
|
|
unsigned long *end)
|
|
{
|
|
if (node->color != color)
|
|
*start += 4096;
|
|
|
|
if (!list_empty(&node->node_list)) {
|
|
node = list_entry(node->node_list.next,
|
|
struct drm_mm_node,
|
|
node_list);
|
|
if (node->allocated && node->color != color)
|
|
*end -= 4096;
|
|
}
|
|
}
|
|
void i915_gem_setup_global_gtt(struct drm_device *dev,
|
|
unsigned long start,
|
|
unsigned long mappable_end,
|
|
unsigned long end)
|
|
{
|
|
/* Let GEM Manage all of the aperture.
|
|
*
|
|
* However, leave one page at the end still bound to the scratch page.
|
|
* There are a number of places where the hardware apparently prefetches
|
|
* past the end of the object, and we've seen multiple hangs with the
|
|
* GPU head pointer stuck in a batchbuffer bound at the last page of the
|
|
* aperture. One page should be enough to keep any prefetching inside
|
|
* of the aperture.
|
|
*/
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
|
|
struct drm_mm_node *entry;
|
|
struct drm_i915_gem_object *obj;
|
|
unsigned long hole_start, hole_end;
|
|
|
|
BUG_ON(mappable_end > end);
|
|
|
|
/* Subtract the guard page ... */
|
|
drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
|
|
if (!HAS_LLC(dev))
|
|
dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
|
|
|
|
/* Mark any preallocated objects as occupied */
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
|
struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
|
|
int ret;
|
|
DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
|
|
i915_gem_obj_ggtt_offset(obj), obj->base.size);
|
|
|
|
WARN_ON(i915_gem_obj_ggtt_bound(obj));
|
|
ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
|
|
if (ret)
|
|
DRM_DEBUG_KMS("Reservation failed\n");
|
|
obj->has_global_gtt_mapping = 1;
|
|
list_add(&vma->vma_link, &obj->vma_list);
|
|
}
|
|
|
|
dev_priv->gtt.base.start = start;
|
|
dev_priv->gtt.base.total = end - start;
|
|
|
|
/* Clear any non-preallocated blocks */
|
|
drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
|
|
const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
|
|
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
|
|
hole_start, hole_end);
|
|
ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count);
|
|
}
|
|
|
|
/* And finally clear the reserved guard page */
|
|
ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1);
|
|
}
|
|
|
|
static bool
|
|
intel_enable_ppgtt(struct drm_device *dev)
|
|
{
|
|
if (i915_enable_ppgtt >= 0)
|
|
return i915_enable_ppgtt;
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
/* Disable ppgtt on SNB if VT-d is on. */
|
|
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
|
return false;
|
|
#endif
|
|
|
|
return true;
|
|
}
|
|
|
|
void i915_gem_init_global_gtt(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
unsigned long gtt_size, mappable_size;
|
|
|
|
gtt_size = dev_priv->gtt.base.total;
|
|
mappable_size = dev_priv->gtt.mappable_end;
|
|
|
|
if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
|
|
int ret;
|
|
|
|
if (INTEL_INFO(dev)->gen <= 7) {
|
|
/* PPGTT pdes are stolen from global gtt ptes, so shrink the
|
|
* aperture accordingly when using aliasing ppgtt. */
|
|
gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
|
|
}
|
|
|
|
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
|
|
|
|
ret = i915_gem_init_aliasing_ppgtt(dev);
|
|
if (!ret)
|
|
return;
|
|
|
|
DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
|
|
drm_mm_takedown(&dev_priv->gtt.base.mm);
|
|
gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
|
|
}
|
|
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
|
|
}
|
|
|
|
static int setup_scratch_page(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct page *page;
|
|
dma_addr_t dma_addr;
|
|
|
|
page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
|
|
if (page == NULL)
|
|
return -ENOMEM;
|
|
get_page(page);
|
|
set_pages_uc(page, 1);
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
if (pci_dma_mapping_error(dev->pdev, dma_addr))
|
|
return -EINVAL;
|
|
#else
|
|
dma_addr = page_to_phys(page);
|
|
#endif
|
|
dev_priv->gtt.base.scratch.page = page;
|
|
dev_priv->gtt.base.scratch.addr = dma_addr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void teardown_scratch_page(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct page *page = dev_priv->gtt.base.scratch.page;
|
|
|
|
set_pages_wb(page, 1);
|
|
pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
put_page(page);
|
|
__free_page(page);
|
|
}
|
|
|
|
static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
|
|
{
|
|
snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
|
|
snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
|
|
return snb_gmch_ctl << 20;
|
|
}
|
|
|
|
static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
|
|
{
|
|
snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
|
|
snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
|
|
return snb_gmch_ctl << 25; /* 32 MB units */
|
|
}
|
|
|
|
static int gen6_gmch_probe(struct drm_device *dev,
|
|
size_t *gtt_total,
|
|
size_t *stolen,
|
|
phys_addr_t *mappable_base,
|
|
unsigned long *mappable_end)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
phys_addr_t gtt_bus_addr;
|
|
unsigned int gtt_size;
|
|
u16 snb_gmch_ctl;
|
|
int ret;
|
|
|
|
*mappable_base = pci_resource_start(dev->pdev, 2);
|
|
*mappable_end = pci_resource_len(dev->pdev, 2);
|
|
|
|
/* 64/512MB is the current min/max we actually know of, but this is just
|
|
* a coarse sanity check.
|
|
*/
|
|
if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
|
|
DRM_ERROR("Unknown GMADR size (%lx)\n",
|
|
dev_priv->gtt.mappable_end);
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
|
|
pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
|
|
pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
|
|
gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
|
|
|
|
*stolen = gen6_get_stolen_size(snb_gmch_ctl);
|
|
*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
|
|
|
|
/* For Modern GENs the PTEs and register space are split in the BAR */
|
|
gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
|
|
(pci_resource_len(dev->pdev, 0) / 2);
|
|
|
|
dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
|
|
if (!dev_priv->gtt.gsm) {
|
|
DRM_ERROR("Failed to map the gtt page table\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = setup_scratch_page(dev);
|
|
if (ret)
|
|
DRM_ERROR("Scratch setup failed\n");
|
|
|
|
dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
|
|
dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void gen6_gmch_remove(struct i915_address_space *vm)
|
|
{
|
|
|
|
struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
|
|
iounmap(gtt->gsm);
|
|
teardown_scratch_page(vm->dev);
|
|
}
|
|
|
|
static int i915_gmch_probe(struct drm_device *dev,
|
|
size_t *gtt_total,
|
|
size_t *stolen,
|
|
phys_addr_t *mappable_base,
|
|
unsigned long *mappable_end)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int ret;
|
|
|
|
ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
|
|
if (!ret) {
|
|
DRM_ERROR("failed to set up gmch\n");
|
|
return -EIO;
|
|
}
|
|
|
|
intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
|
|
|
|
dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
|
|
dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
|
|
dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void i915_gmch_remove(struct i915_address_space *vm)
|
|
{
|
|
intel_gmch_remove();
|
|
}
|
|
|
|
int i915_gem_gtt_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct i915_gtt *gtt = &dev_priv->gtt;
|
|
int ret;
|
|
|
|
if (INTEL_INFO(dev)->gen <= 5) {
|
|
gtt->gtt_probe = i915_gmch_probe;
|
|
gtt->base.cleanup = i915_gmch_remove;
|
|
} else {
|
|
gtt->gtt_probe = gen6_gmch_probe;
|
|
gtt->base.cleanup = gen6_gmch_remove;
|
|
if (IS_HASWELL(dev) && dev_priv->ellc_size)
|
|
gtt->base.pte_encode = iris_pte_encode;
|
|
else if (IS_HASWELL(dev))
|
|
gtt->base.pte_encode = hsw_pte_encode;
|
|
else if (IS_VALLEYVIEW(dev))
|
|
gtt->base.pte_encode = byt_pte_encode;
|
|
else if (INTEL_INFO(dev)->gen >= 7)
|
|
gtt->base.pte_encode = ivb_pte_encode;
|
|
else
|
|
gtt->base.pte_encode = snb_pte_encode;
|
|
}
|
|
|
|
ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
|
|
>t->mappable_base, >t->mappable_end);
|
|
if (ret)
|
|
return ret;
|
|
|
|
gtt->base.dev = dev;
|
|
|
|
/* GMADR is the PCI mmio aperture into the global GTT. */
|
|
DRM_INFO("Memory usable by graphics device = %zdM\n",
|
|
gtt->base.total >> 20);
|
|
DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
|
|
DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
|
|
|
|
return 0;
|
|
}
|