![]() The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> |
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.. | ||
phy | ||
pll | ||
dsi.c | ||
dsi.h | ||
dsi.xml.h | ||
dsi_cfg.c | ||
dsi_cfg.h | ||
dsi_host.c | ||
dsi_manager.c | ||
mmss_cc.xml.h | ||
sfpb.xml.h |