![Thierry Reding](/assets/img/avatar_default.png)
Non-legacy drivers should only use this API to allow per-CRTC data to be eventually moved into struct drm_crtc. Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Vincent Abriou <vincent.abriou@st.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
649 lines
17 KiB
C
649 lines
17 KiB
C
/*
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* Copyright (C) STMicroelectronics SA 2014
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* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include "sti_compositor.h"
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#include "sti_gdp.h"
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#include "sti_plane.h"
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#include "sti_vtg.h"
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#define ALPHASWITCH BIT(6)
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#define ENA_COLOR_FILL BIT(8)
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#define BIGNOTLITTLE BIT(23)
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#define WAIT_NEXT_VSYNC BIT(31)
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/* GDP color formats */
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#define GDP_RGB565 0x00
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#define GDP_RGB888 0x01
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#define GDP_RGB888_32 0x02
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#define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
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#define GDP_ARGB8565 0x04
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#define GDP_ARGB8888 0x05
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#define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
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#define GDP_ARGB1555 0x06
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#define GDP_ARGB4444 0x07
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#define GDP_CLUT8 0x0B
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#define GDP_YCBR888 0x10
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#define GDP_YCBR422R 0x12
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#define GDP_AYCBR8888 0x15
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#define GAM_GDP_CTL_OFFSET 0x00
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#define GAM_GDP_AGC_OFFSET 0x04
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#define GAM_GDP_VPO_OFFSET 0x0C
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#define GAM_GDP_VPS_OFFSET 0x10
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#define GAM_GDP_PML_OFFSET 0x14
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#define GAM_GDP_PMP_OFFSET 0x18
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#define GAM_GDP_SIZE_OFFSET 0x1C
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#define GAM_GDP_NVN_OFFSET 0x24
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#define GAM_GDP_KEY1_OFFSET 0x28
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#define GAM_GDP_KEY2_OFFSET 0x2C
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#define GAM_GDP_PPT_OFFSET 0x34
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#define GAM_GDP_CML_OFFSET 0x3C
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#define GAM_GDP_MST_OFFSET 0x68
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#define GAM_GDP_ALPHARANGE_255 BIT(5)
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#define GAM_GDP_AGC_FULL_RANGE 0x00808080
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#define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
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#define GAM_GDP_SIZE_MAX 0x7FF
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#define GDP_NODE_NB_BANK 2
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#define GDP_NODE_PER_FIELD 2
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struct sti_gdp_node {
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u32 gam_gdp_ctl;
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u32 gam_gdp_agc;
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u32 reserved1;
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u32 gam_gdp_vpo;
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u32 gam_gdp_vps;
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u32 gam_gdp_pml;
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u32 gam_gdp_pmp;
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u32 gam_gdp_size;
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u32 reserved2;
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u32 gam_gdp_nvn;
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u32 gam_gdp_key1;
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u32 gam_gdp_key2;
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u32 reserved3;
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u32 gam_gdp_ppt;
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u32 reserved4;
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u32 gam_gdp_cml;
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};
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struct sti_gdp_node_list {
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struct sti_gdp_node *top_field;
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dma_addr_t top_field_paddr;
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struct sti_gdp_node *btm_field;
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dma_addr_t btm_field_paddr;
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};
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/**
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* STI GDP structure
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*
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* @sti_plane: sti_plane structure
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* @dev: driver device
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* @regs: gdp registers
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* @clk_pix: pixel clock for the current gdp
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* @clk_main_parent: gdp parent clock if main path used
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* @clk_aux_parent: gdp parent clock if aux path used
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* @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
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* @is_curr_top: true if the current node processed is the top field
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* @node_list: array of node list
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*/
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struct sti_gdp {
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struct sti_plane plane;
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struct device *dev;
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void __iomem *regs;
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struct clk *clk_pix;
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struct clk *clk_main_parent;
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struct clk *clk_aux_parent;
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struct notifier_block vtg_field_nb;
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bool is_curr_top;
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struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
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};
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#define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
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static const uint32_t gdp_supported_formats[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_AYUV,
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DRM_FORMAT_YUV444,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_C8,
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};
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static int sti_gdp_fourcc2format(int fourcc)
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{
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switch (fourcc) {
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case DRM_FORMAT_XRGB8888:
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return GDP_RGB888_32;
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case DRM_FORMAT_XBGR8888:
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return GDP_XBGR8888;
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case DRM_FORMAT_ARGB8888:
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return GDP_ARGB8888;
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case DRM_FORMAT_ABGR8888:
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return GDP_ABGR8888;
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case DRM_FORMAT_ARGB4444:
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return GDP_ARGB4444;
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case DRM_FORMAT_ARGB1555:
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return GDP_ARGB1555;
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case DRM_FORMAT_RGB565:
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return GDP_RGB565;
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case DRM_FORMAT_RGB888:
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return GDP_RGB888;
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case DRM_FORMAT_AYUV:
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return GDP_AYCBR8888;
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case DRM_FORMAT_YUV444:
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return GDP_YCBR888;
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case DRM_FORMAT_VYUY:
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return GDP_YCBR422R;
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case DRM_FORMAT_C8:
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return GDP_CLUT8;
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}
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return -1;
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}
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static int sti_gdp_get_alpharange(int format)
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{
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switch (format) {
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case GDP_ARGB8565:
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case GDP_ARGB8888:
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case GDP_AYCBR8888:
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case GDP_ABGR8888:
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return GAM_GDP_ALPHARANGE_255;
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}
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return 0;
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}
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/**
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* sti_gdp_get_free_nodes
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* @gdp: gdp pointer
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*
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* Look for a GDP node list that is not currently read by the HW.
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*
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* RETURNS:
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* Pointer to the free GDP node list
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*/
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static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
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{
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int hw_nvn;
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unsigned int i;
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hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
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if (!hw_nvn)
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goto end;
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for (i = 0; i < GDP_NODE_NB_BANK; i++)
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if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
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(hw_nvn != gdp->node_list[i].top_field_paddr))
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return &gdp->node_list[i];
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/* in hazardious cases restart with the first node */
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DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
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sti_plane_to_str(&gdp->plane), hw_nvn);
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end:
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return &gdp->node_list[0];
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}
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/**
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* sti_gdp_get_current_nodes
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* @gdp: gdp pointer
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*
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* Look for GDP nodes that are currently read by the HW.
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*
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* RETURNS:
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* Pointer to the current GDP node list
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*/
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static
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struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
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{
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int hw_nvn;
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unsigned int i;
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hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
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if (!hw_nvn)
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goto end;
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for (i = 0; i < GDP_NODE_NB_BANK; i++)
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if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
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(hw_nvn == gdp->node_list[i].top_field_paddr))
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return &gdp->node_list[i];
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end:
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DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
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hw_nvn, sti_plane_to_str(&gdp->plane));
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return NULL;
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}
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/**
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* sti_gdp_disable
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* @gdp: gdp pointer
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*
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* Disable a GDP.
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*/
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static void sti_gdp_disable(struct sti_gdp *gdp)
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{
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struct drm_plane *drm_plane = &gdp->plane.drm_plane;
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struct sti_mixer *mixer = to_sti_mixer(drm_plane->crtc);
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struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
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unsigned int i;
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DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
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/* Set the nodes as 'to be ignored on mixer' */
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for (i = 0; i < GDP_NODE_NB_BANK; i++) {
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gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
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gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
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}
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if (sti_vtg_unregister_client(mixer->id == STI_MIXER_MAIN ?
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compo->vtg_main : compo->vtg_aux, &gdp->vtg_field_nb))
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DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
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if (gdp->clk_pix)
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clk_disable_unprepare(gdp->clk_pix);
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gdp->plane.status = STI_PLANE_DISABLED;
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}
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/**
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* sti_gdp_field_cb
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* @nb: notifier block
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* @event: event message
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* @data: private data
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*
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* Handle VTG top field and bottom field event.
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*
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* RETURNS:
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* 0 on success.
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*/
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int sti_gdp_field_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
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if (gdp->plane.status == STI_PLANE_FLUSHING) {
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/* disable need to be synchronize on vsync event */
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DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
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sti_plane_to_str(&gdp->plane));
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sti_gdp_disable(gdp);
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}
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switch (event) {
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case VTG_TOP_FIELD_EVENT:
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gdp->is_curr_top = true;
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break;
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case VTG_BOTTOM_FIELD_EVENT:
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gdp->is_curr_top = false;
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break;
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default:
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DRM_ERROR("unsupported event: %lu\n", event);
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break;
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}
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return 0;
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}
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static void sti_gdp_init(struct sti_gdp *gdp)
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{
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struct device_node *np = gdp->dev->of_node;
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dma_addr_t dma_addr;
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void *base;
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unsigned int i, size;
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/* Allocate all the nodes within a single memory page */
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size = sizeof(struct sti_gdp_node) *
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GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
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base = dma_alloc_writecombine(gdp->dev,
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size, &dma_addr, GFP_KERNEL | GFP_DMA);
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if (!base) {
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DRM_ERROR("Failed to allocate memory for GDP node\n");
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return;
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}
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memset(base, 0, size);
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for (i = 0; i < GDP_NODE_NB_BANK; i++) {
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if (dma_addr & 0xF) {
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DRM_ERROR("Mem alignment failed\n");
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return;
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}
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gdp->node_list[i].top_field = base;
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gdp->node_list[i].top_field_paddr = dma_addr;
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DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
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base += sizeof(struct sti_gdp_node);
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dma_addr += sizeof(struct sti_gdp_node);
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if (dma_addr & 0xF) {
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DRM_ERROR("Mem alignment failed\n");
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return;
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}
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gdp->node_list[i].btm_field = base;
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gdp->node_list[i].btm_field_paddr = dma_addr;
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DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
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base += sizeof(struct sti_gdp_node);
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dma_addr += sizeof(struct sti_gdp_node);
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}
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if (of_device_is_compatible(np, "st,stih407-compositor")) {
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/* GDP of STiH407 chip have its own pixel clock */
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char *clk_name;
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switch (gdp->plane.desc) {
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case STI_GDP_0:
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clk_name = "pix_gdp1";
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break;
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case STI_GDP_1:
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clk_name = "pix_gdp2";
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break;
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case STI_GDP_2:
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clk_name = "pix_gdp3";
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break;
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case STI_GDP_3:
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clk_name = "pix_gdp4";
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break;
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default:
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DRM_ERROR("GDP id not recognized\n");
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return;
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}
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gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
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if (IS_ERR(gdp->clk_pix))
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DRM_ERROR("Cannot get %s clock\n", clk_name);
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gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
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if (IS_ERR(gdp->clk_main_parent))
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DRM_ERROR("Cannot get main_parent clock\n");
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gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
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if (IS_ERR(gdp->clk_aux_parent))
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DRM_ERROR("Cannot get aux_parent clock\n");
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}
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}
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static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
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struct drm_plane_state *oldstate)
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{
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struct drm_plane_state *state = drm_plane->state;
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struct sti_plane *plane = to_sti_plane(drm_plane);
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struct sti_gdp *gdp = to_sti_gdp(plane);
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struct drm_crtc *crtc = state->crtc;
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struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
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struct drm_framebuffer *fb = state->fb;
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bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false;
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struct sti_mixer *mixer;
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struct drm_display_mode *mode;
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int dst_x, dst_y, dst_w, dst_h;
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int src_x, src_y, src_w, src_h;
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struct drm_gem_cma_object *cma_obj;
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struct sti_gdp_node_list *list;
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struct sti_gdp_node_list *curr_list;
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struct sti_gdp_node *top_field, *btm_field;
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u32 dma_updated_top;
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u32 dma_updated_btm;
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int format;
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unsigned int depth, bpp;
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u32 ydo, xdo, yds, xds;
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int res;
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/* Manage the case where crtc is null (disabled) */
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if (!crtc)
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return;
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mixer = to_sti_mixer(crtc);
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mode = &crtc->mode;
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dst_x = state->crtc_x;
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dst_y = state->crtc_y;
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dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
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dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
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/* src_x are in 16.16 format */
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src_x = state->src_x >> 16;
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src_y = state->src_y >> 16;
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src_w = state->src_w >> 16;
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src_h = state->src_h >> 16;
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DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
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crtc->base.id, sti_mixer_to_str(mixer),
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drm_plane->base.id, sti_plane_to_str(plane));
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DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
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sti_plane_to_str(plane),
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dst_w, dst_h, dst_x, dst_y,
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src_w, src_h, src_x, src_y);
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list = sti_gdp_get_free_nodes(gdp);
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top_field = list->top_field;
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btm_field = list->btm_field;
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dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
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sti_plane_to_str(plane), top_field, btm_field);
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/* build the top field */
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top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
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top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
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format = sti_gdp_fourcc2format(fb->pixel_format);
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if (format == -1) {
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DRM_ERROR("Format not supported by GDP %.4s\n",
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(char *)&fb->pixel_format);
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return;
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}
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top_field->gam_gdp_ctl |= format;
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top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
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top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
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cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
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if (!cma_obj) {
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DRM_ERROR("Can't get CMA GEM object for fb\n");
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return;
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}
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DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
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(char *)&fb->pixel_format,
|
|
(unsigned long)cma_obj->paddr);
|
|
|
|
/* pixel memory location */
|
|
drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
|
|
top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
|
|
top_field->gam_gdp_pml += src_x * (bpp >> 3);
|
|
top_field->gam_gdp_pml += src_y * fb->pitches[0];
|
|
|
|
/* input parameters */
|
|
top_field->gam_gdp_pmp = fb->pitches[0];
|
|
top_field->gam_gdp_size = clamp_val(src_h, 0, GAM_GDP_SIZE_MAX) << 16 |
|
|
clamp_val(src_w, 0, GAM_GDP_SIZE_MAX);
|
|
|
|
/* output parameters */
|
|
ydo = sti_vtg_get_line_number(*mode, dst_y);
|
|
yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
|
|
xdo = sti_vtg_get_pixel_number(*mode, dst_x);
|
|
xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
|
|
top_field->gam_gdp_vpo = (ydo << 16) | xdo;
|
|
top_field->gam_gdp_vps = (yds << 16) | xds;
|
|
|
|
/* Same content and chained together */
|
|
memcpy(btm_field, top_field, sizeof(*btm_field));
|
|
top_field->gam_gdp_nvn = list->btm_field_paddr;
|
|
btm_field->gam_gdp_nvn = list->top_field_paddr;
|
|
|
|
/* Interlaced mode */
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
|
|
fb->pitches[0];
|
|
|
|
if (first_prepare) {
|
|
/* Register gdp callback */
|
|
if (sti_vtg_register_client(mixer->id == STI_MIXER_MAIN ?
|
|
compo->vtg_main : compo->vtg_aux,
|
|
&gdp->vtg_field_nb, crtc)) {
|
|
DRM_ERROR("Cannot register VTG notifier\n");
|
|
return;
|
|
}
|
|
|
|
/* Set and enable gdp clock */
|
|
if (gdp->clk_pix) {
|
|
struct clk *clkp;
|
|
int rate = mode->clock * 1000;
|
|
|
|
/* According to the mixer used, the gdp pixel clock
|
|
* should have a different parent clock. */
|
|
if (mixer->id == STI_MIXER_MAIN)
|
|
clkp = gdp->clk_main_parent;
|
|
else
|
|
clkp = gdp->clk_aux_parent;
|
|
|
|
if (clkp)
|
|
clk_set_parent(gdp->clk_pix, clkp);
|
|
|
|
res = clk_set_rate(gdp->clk_pix, rate);
|
|
if (res < 0) {
|
|
DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
|
|
rate);
|
|
return;
|
|
}
|
|
|
|
if (clk_prepare_enable(gdp->clk_pix)) {
|
|
DRM_ERROR("Failed to prepare/enable gdp\n");
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the NVN field of the 'right' field of the current GDP node
|
|
* (being used by the HW) with the address of the updated ('free') top
|
|
* field GDP node.
|
|
* - In interlaced mode the 'right' field is the bottom field as we
|
|
* update frames starting from their top field
|
|
* - In progressive mode, we update both bottom and top fields which
|
|
* are equal nodes.
|
|
* At the next VSYNC, the updated node list will be used by the HW.
|
|
*/
|
|
curr_list = sti_gdp_get_current_nodes(gdp);
|
|
dma_updated_top = list->top_field_paddr;
|
|
dma_updated_btm = list->btm_field_paddr;
|
|
|
|
dev_dbg(gdp->dev, "Current NVN:0x%X\n",
|
|
readl(gdp->regs + GAM_GDP_NVN_OFFSET));
|
|
dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
|
|
(unsigned long)cma_obj->paddr,
|
|
readl(gdp->regs + GAM_GDP_PML_OFFSET));
|
|
|
|
if (!curr_list) {
|
|
/* First update or invalid node should directly write in the
|
|
* hw register */
|
|
DRM_DEBUG_DRIVER("%s first update (or invalid node)",
|
|
sti_plane_to_str(plane));
|
|
|
|
writel(gdp->is_curr_top ?
|
|
dma_updated_btm : dma_updated_top,
|
|
gdp->regs + GAM_GDP_NVN_OFFSET);
|
|
goto end;
|
|
}
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
if (gdp->is_curr_top) {
|
|
/* Do not update in the middle of the frame, but
|
|
* postpone the update after the bottom field has
|
|
* been displayed */
|
|
curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
|
|
} else {
|
|
/* Direct update to avoid one frame delay */
|
|
writel(dma_updated_top,
|
|
gdp->regs + GAM_GDP_NVN_OFFSET);
|
|
}
|
|
} else {
|
|
/* Direct update for progressive to avoid one frame delay */
|
|
writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
|
|
}
|
|
|
|
end:
|
|
plane->status = STI_PLANE_UPDATED;
|
|
}
|
|
|
|
static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
|
|
struct drm_plane_state *oldstate)
|
|
{
|
|
struct sti_plane *plane = to_sti_plane(drm_plane);
|
|
struct sti_mixer *mixer = to_sti_mixer(drm_plane->crtc);
|
|
|
|
if (!drm_plane->crtc) {
|
|
DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
|
|
drm_plane->base.id);
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
|
|
drm_plane->crtc->base.id, sti_mixer_to_str(mixer),
|
|
drm_plane->base.id, sti_plane_to_str(plane));
|
|
|
|
plane->status = STI_PLANE_DISABLING;
|
|
}
|
|
|
|
static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
|
|
.atomic_update = sti_gdp_atomic_update,
|
|
.atomic_disable = sti_gdp_atomic_disable,
|
|
};
|
|
|
|
struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
|
|
struct device *dev, int desc,
|
|
void __iomem *baseaddr,
|
|
unsigned int possible_crtcs,
|
|
enum drm_plane_type type)
|
|
{
|
|
struct sti_gdp *gdp;
|
|
int res;
|
|
|
|
gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
|
|
if (!gdp) {
|
|
DRM_ERROR("Failed to allocate memory for GDP\n");
|
|
return NULL;
|
|
}
|
|
|
|
gdp->dev = dev;
|
|
gdp->regs = baseaddr;
|
|
gdp->plane.desc = desc;
|
|
gdp->plane.status = STI_PLANE_DISABLED;
|
|
|
|
gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
|
|
|
|
sti_gdp_init(gdp);
|
|
|
|
res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
|
|
possible_crtcs,
|
|
&sti_plane_helpers_funcs,
|
|
gdp_supported_formats,
|
|
ARRAY_SIZE(gdp_supported_formats),
|
|
type);
|
|
if (res) {
|
|
DRM_ERROR("Failed to initialize universal plane\n");
|
|
goto err;
|
|
}
|
|
|
|
drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
|
|
|
|
sti_plane_init_property(&gdp->plane, type);
|
|
|
|
return &gdp->plane.drm_plane;
|
|
|
|
err:
|
|
devm_kfree(dev, gdp);
|
|
return NULL;
|
|
}
|