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alistair23-linux/drivers/pinctrl/freescale/pinctrl-s32v234.c

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* s32v234 pinctrl driver based on imx pinmux and pinconf core
*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-s32v.h"
enum s32v234_pins {
S32V234_MSCR_PA0 = 0,
S32V234_MSCR_PA1 = 1,
S32V234_MSCR_PA2 = 2,
S32V234_MSCR_PA3 = 3,
S32V234_MSCR_PA4 = 4,
S32V234_MSCR_PA5 = 5,
S32V234_MSCR_PA6 = 6,
S32V234_MSCR_PA7 = 7,
S32V234_MSCR_PA8 = 8,
S32V234_MSCR_PA9 = 9,
S32V234_MSCR_PA10 = 10,
S32V234_MSCR_PA11 = 11,
S32V234_MSCR_PA12 = 12,
S32V234_MSCR_PA13 = 13,
S32V234_MSCR_PA14 = 14,
S32V234_MSCR_PA15 = 15,
S32V234_MSCR_PB0 = 16,
S32V234_MSCR_PB1 = 17,
S32V234_MSCR_PB2 = 18,
S32V234_MSCR_PB3 = 19,
S32V234_MSCR_PB4 = 20,
S32V234_MSCR_PB5 = 21,
S32V234_MSCR_PB6 = 22,
S32V234_MSCR_PB7 = 23,
S32V234_MSCR_PB8 = 24,
S32V234_MSCR_PB9 = 25,
S32V234_MSCR_PB10 = 26,
S32V234_MSCR_PB11 = 27,
S32V234_MSCR_PB12 = 28,
S32V234_MSCR_PB13 = 29,
S32V234_MSCR_PB14 = 30,
S32V234_MSCR_PB15 = 31,
S32V234_MSCR_PC0 = 32,
S32V234_MSCR_PC1 = 33,
S32V234_MSCR_PC2 = 34,
S32V234_MSCR_PC3 = 35,
S32V234_MSCR_PC4 = 36,
S32V234_MSCR_PC5 = 37,
S32V234_MSCR_PC6 = 38,
S32V234_MSCR_PC7 = 39,
S32V234_MSCR_PC8 = 40,
S32V234_MSCR_PC9 = 41,
S32V234_MSCR_PC10 = 42,
S32V234_MSCR_PC11 = 43,
S32V234_MSCR_PC12 = 44,
S32V234_MSCR_PC13 = 45,
S32V234_MSCR_PC14 = 46,
S32V234_MSCR_PC15 = 47,
S32V234_MSCR_PD0 = 48,
S32V234_MSCR_PD1 = 49,
S32V234_MSCR_PD2 = 50,
S32V234_MSCR_PD3 = 51,
S32V234_MSCR_PD4 = 52,
S32V234_MSCR_PD5 = 53,
S32V234_MSCR_PD6 = 54,
S32V234_MSCR_PD7 = 55,
S32V234_MSCR_PD8 = 56,
S32V234_MSCR_PD9 = 57,
S32V234_MSCR_PD10 = 58,
S32V234_MSCR_PD11 = 59,
S32V234_MSCR_PD12 = 60,
S32V234_MSCR_PD13 = 61,
S32V234_MSCR_PD14 = 62,
S32V234_MSCR_PD15 = 63,
S32V234_MSCR_PE0 = 64,
S32V234_MSCR_PE1 = 65,
S32V234_MSCR_PE2 = 66,
S32V234_MSCR_PE3 = 67,
S32V234_MSCR_PE4 = 68,
S32V234_MSCR_PE5 = 69,
S32V234_MSCR_PE6 = 70,
S32V234_MSCR_PE7 = 71,
S32V234_MSCR_PE8 = 72,
S32V234_MSCR_PE9 = 73,
S32V234_MSCR_PE10 = 74,
S32V234_MSCR_PE11 = 75,
S32V234_MSCR_PE12 = 76,
S32V234_MSCR_PE13 = 77,
S32V234_MSCR_PE14 = 78,
S32V234_MSCR_PE15 = 79,
S32V234_MSCR_PF0 = 80,
S32V234_MSCR_PF1 = 81,
S32V234_MSCR_PF2 = 82,
S32V234_MSCR_PF3 = 83,
S32V234_MSCR_PF4 = 84,
S32V234_MSCR_PF5 = 85,
S32V234_MSCR_PF6 = 86,
S32V234_MSCR_PF7 = 87,
S32V234_MSCR_PF8 = 88,
S32V234_MSCR_PF9 = 89,
S32V234_MSCR_PF10 = 90,
S32V234_MSCR_PF11 = 91,
S32V234_MSCR_PF12 = 92,
S32V234_MSCR_PF13 = 93,
S32V234_MSCR_PF14 = 94,
S32V234_MSCR_PF15 = 95,
S32V234_MSCR_PG0 = 96,
S32V234_MSCR_PG1 = 97,
S32V234_MSCR_PG2 = 98,
S32V234_MSCR_PG3 = 99,
S32V234_MSCR_PG4 = 100,
S32V234_MSCR_PG5 = 101,
S32V234_MSCR_PG6 = 102,
S32V234_MSCR_PG7 = 103,
S32V234_MSCR_PG8 = 104,
S32V234_MSCR_PG9 = 105,
S32V234_MSCR_PG10 = 106,
S32V234_MSCR_PG11 = 107,
S32V234_MSCR_PG12 = 108,
S32V234_MSCR_PG13 = 109,
S32V234_MSCR_PG14 = 110,
S32V234_MSCR_PG15 = 111,
S32V234_MSCR_PH0 = 112,
S32V234_MSCR_PH1 = 113,
S32V234_MSCR_PH2 = 114,
S32V234_MSCR_PH3 = 115,
S32V234_MSCR_PH4 = 116,
S32V234_MSCR_PH5 = 117,
S32V234_MSCR_PH6 = 118,
S32V234_MSCR_PH7 = 119,
S32V234_MSCR_PH8 = 120,
S32V234_MSCR_PH9 = 121,
S32V234_MSCR_PH10 = 122,
S32V234_MSCR_PH11 = 123,
S32V234_MSCR_PH12 = 124,
S32V234_MSCR_PH13 = 125,
S32V234_MSCR_PH14 = 126,
S32V234_MSCR_PH15 = 127,
S32V234_MSCR_PJ0 = 128,
S32V234_MSCR_PJ1 = 129,
S32V234_MSCR_PJ2 = 130,
S32V234_MSCR_PJ3 = 131,
S32V234_MSCR_PJ4 = 132,
S32V234_MSCR_PJ5 = 133,
S32V234_MSCR_PJ6 = 134,
S32V234_MSCR_PJ7 = 135,
S32V234_MSCR_PJ8 = 136,
S32V234_MSCR_PJ9 = 137,
S32V234_MSCR_PJ10 = 138,
S32V234_MSCR_PJ11 = 139,
S32V234_MSCR_PJ12 = 140,
S32V234_MSCR_PJ13 = 141,
S32V234_MSCR_PJ14 = 142,
S32V234_MSCR_PJ15 = 143,
S32V234_MSCR_PK0 = 144,
S32V234_MSCR_PK1 = 145,
S32V234_MSCR_PK2 = 146,
S32V234_MSCR_PK3 = 147,
S32V234_MSCR_PK4 = 148,
S32V234_MSCR_PK5 = 149,
S32V234_MSCR_PK6 = 150,
S32V234_MSCR_PK7 = 151,
S32V234_MSCR_PK8 = 152,
S32V234_MSCR_PK9 = 153,
S32V234_MSCR_PK10 = 154,
S32V234_MSCR_PK11 = 155,
S32V234_MSCR_PK12 = 156,
S32V234_MSCR_PK13 = 157,
S32V234_MSCR_PK14 = 158,
S32V234_MSCR_PK15 = 159,
S32V234_MSCR_PL0 = 160,
S32V234_MSCR_PL1 = 161,
S32V234_MSCR_PL2 = 162,
S32V234_MSCR_PL3 = 163,
S32V234_MSCR_PL4 = 164,
S32V234_MSCR_PL5 = 165,
S32V234_MSCR_PL8 = 166,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc s32v234_pinctrl_pads[] = {
S32V_PINCTRL_PIN(S32V234_MSCR_PA0),
S32V_PINCTRL_PIN(S32V234_MSCR_PA1),
S32V_PINCTRL_PIN(S32V234_MSCR_PA2),
S32V_PINCTRL_PIN(S32V234_MSCR_PA3),
S32V_PINCTRL_PIN(S32V234_MSCR_PA4),
S32V_PINCTRL_PIN(S32V234_MSCR_PA5),
S32V_PINCTRL_PIN(S32V234_MSCR_PA6),
S32V_PINCTRL_PIN(S32V234_MSCR_PA7),
S32V_PINCTRL_PIN(S32V234_MSCR_PA8),
S32V_PINCTRL_PIN(S32V234_MSCR_PA9),
S32V_PINCTRL_PIN(S32V234_MSCR_PA10),
S32V_PINCTRL_PIN(S32V234_MSCR_PA11),
S32V_PINCTRL_PIN(S32V234_MSCR_PA12),
S32V_PINCTRL_PIN(S32V234_MSCR_PA13),
S32V_PINCTRL_PIN(S32V234_MSCR_PA14),
S32V_PINCTRL_PIN(S32V234_MSCR_PA15),
S32V_PINCTRL_PIN(S32V234_MSCR_PB0),
S32V_PINCTRL_PIN(S32V234_MSCR_PB1),
S32V_PINCTRL_PIN(S32V234_MSCR_PB2),
S32V_PINCTRL_PIN(S32V234_MSCR_PB3),
S32V_PINCTRL_PIN(S32V234_MSCR_PB4),
S32V_PINCTRL_PIN(S32V234_MSCR_PB5),
S32V_PINCTRL_PIN(S32V234_MSCR_PB6),
S32V_PINCTRL_PIN(S32V234_MSCR_PB7),
S32V_PINCTRL_PIN(S32V234_MSCR_PB8),
S32V_PINCTRL_PIN(S32V234_MSCR_PB9),
S32V_PINCTRL_PIN(S32V234_MSCR_PB10),
S32V_PINCTRL_PIN(S32V234_MSCR_PB11),
S32V_PINCTRL_PIN(S32V234_MSCR_PB12),
S32V_PINCTRL_PIN(S32V234_MSCR_PB13),
S32V_PINCTRL_PIN(S32V234_MSCR_PB14),
S32V_PINCTRL_PIN(S32V234_MSCR_PB15),
S32V_PINCTRL_PIN(S32V234_MSCR_PC0),
S32V_PINCTRL_PIN(S32V234_MSCR_PC1),
S32V_PINCTRL_PIN(S32V234_MSCR_PC2),
S32V_PINCTRL_PIN(S32V234_MSCR_PC3),
S32V_PINCTRL_PIN(S32V234_MSCR_PC4),
S32V_PINCTRL_PIN(S32V234_MSCR_PC5),
S32V_PINCTRL_PIN(S32V234_MSCR_PC6),
S32V_PINCTRL_PIN(S32V234_MSCR_PC7),
S32V_PINCTRL_PIN(S32V234_MSCR_PC8),
S32V_PINCTRL_PIN(S32V234_MSCR_PC9),
S32V_PINCTRL_PIN(S32V234_MSCR_PC10),
S32V_PINCTRL_PIN(S32V234_MSCR_PC11),
S32V_PINCTRL_PIN(S32V234_MSCR_PC12),
S32V_PINCTRL_PIN(S32V234_MSCR_PC13),
S32V_PINCTRL_PIN(S32V234_MSCR_PC14),
S32V_PINCTRL_PIN(S32V234_MSCR_PC15),
S32V_PINCTRL_PIN(S32V234_MSCR_PD0),
S32V_PINCTRL_PIN(S32V234_MSCR_PD1),
S32V_PINCTRL_PIN(S32V234_MSCR_PD2),
S32V_PINCTRL_PIN(S32V234_MSCR_PD3),
S32V_PINCTRL_PIN(S32V234_MSCR_PD4),
S32V_PINCTRL_PIN(S32V234_MSCR_PD5),
S32V_PINCTRL_PIN(S32V234_MSCR_PD6),
S32V_PINCTRL_PIN(S32V234_MSCR_PD7),
S32V_PINCTRL_PIN(S32V234_MSCR_PD8),
S32V_PINCTRL_PIN(S32V234_MSCR_PD9),
S32V_PINCTRL_PIN(S32V234_MSCR_PD10),
S32V_PINCTRL_PIN(S32V234_MSCR_PD11),
S32V_PINCTRL_PIN(S32V234_MSCR_PD12),
S32V_PINCTRL_PIN(S32V234_MSCR_PD13),
S32V_PINCTRL_PIN(S32V234_MSCR_PD14),
S32V_PINCTRL_PIN(S32V234_MSCR_PD15),
S32V_PINCTRL_PIN(S32V234_MSCR_PE0),
S32V_PINCTRL_PIN(S32V234_MSCR_PE1),
S32V_PINCTRL_PIN(S32V234_MSCR_PE2),
S32V_PINCTRL_PIN(S32V234_MSCR_PE3),
S32V_PINCTRL_PIN(S32V234_MSCR_PE4),
S32V_PINCTRL_PIN(S32V234_MSCR_PE5),
S32V_PINCTRL_PIN(S32V234_MSCR_PE6),
S32V_PINCTRL_PIN(S32V234_MSCR_PE7),
S32V_PINCTRL_PIN(S32V234_MSCR_PE8),
S32V_PINCTRL_PIN(S32V234_MSCR_PE9),
S32V_PINCTRL_PIN(S32V234_MSCR_PE10),
S32V_PINCTRL_PIN(S32V234_MSCR_PE11),
S32V_PINCTRL_PIN(S32V234_MSCR_PE12),
S32V_PINCTRL_PIN(S32V234_MSCR_PE13),
S32V_PINCTRL_PIN(S32V234_MSCR_PE14),
S32V_PINCTRL_PIN(S32V234_MSCR_PE15),
S32V_PINCTRL_PIN(S32V234_MSCR_PF0),
S32V_PINCTRL_PIN(S32V234_MSCR_PF1),
S32V_PINCTRL_PIN(S32V234_MSCR_PF2),
S32V_PINCTRL_PIN(S32V234_MSCR_PF3),
S32V_PINCTRL_PIN(S32V234_MSCR_PF4),
S32V_PINCTRL_PIN(S32V234_MSCR_PF5),
S32V_PINCTRL_PIN(S32V234_MSCR_PF6),
S32V_PINCTRL_PIN(S32V234_MSCR_PF7),
S32V_PINCTRL_PIN(S32V234_MSCR_PF8),
S32V_PINCTRL_PIN(S32V234_MSCR_PF9),
S32V_PINCTRL_PIN(S32V234_MSCR_PF10),
S32V_PINCTRL_PIN(S32V234_MSCR_PF11),
S32V_PINCTRL_PIN(S32V234_MSCR_PF12),
S32V_PINCTRL_PIN(S32V234_MSCR_PF13),
S32V_PINCTRL_PIN(S32V234_MSCR_PF14),
S32V_PINCTRL_PIN(S32V234_MSCR_PF15),
S32V_PINCTRL_PIN(S32V234_MSCR_PG0),
S32V_PINCTRL_PIN(S32V234_MSCR_PG1),
S32V_PINCTRL_PIN(S32V234_MSCR_PG2),
S32V_PINCTRL_PIN(S32V234_MSCR_PG3),
S32V_PINCTRL_PIN(S32V234_MSCR_PG4),
S32V_PINCTRL_PIN(S32V234_MSCR_PG5),
S32V_PINCTRL_PIN(S32V234_MSCR_PG6),
S32V_PINCTRL_PIN(S32V234_MSCR_PG7),
S32V_PINCTRL_PIN(S32V234_MSCR_PG8),
S32V_PINCTRL_PIN(S32V234_MSCR_PG9),
S32V_PINCTRL_PIN(S32V234_MSCR_PG10),
S32V_PINCTRL_PIN(S32V234_MSCR_PG11),
S32V_PINCTRL_PIN(S32V234_MSCR_PG12),
S32V_PINCTRL_PIN(S32V234_MSCR_PG13),
S32V_PINCTRL_PIN(S32V234_MSCR_PG14),
S32V_PINCTRL_PIN(S32V234_MSCR_PG15),
S32V_PINCTRL_PIN(S32V234_MSCR_PH0),
S32V_PINCTRL_PIN(S32V234_MSCR_PH1),
S32V_PINCTRL_PIN(S32V234_MSCR_PH2),
S32V_PINCTRL_PIN(S32V234_MSCR_PH3),
S32V_PINCTRL_PIN(S32V234_MSCR_PH4),
S32V_PINCTRL_PIN(S32V234_MSCR_PH5),
S32V_PINCTRL_PIN(S32V234_MSCR_PH6),
S32V_PINCTRL_PIN(S32V234_MSCR_PH7),
S32V_PINCTRL_PIN(S32V234_MSCR_PH8),
S32V_PINCTRL_PIN(S32V234_MSCR_PH9),
S32V_PINCTRL_PIN(S32V234_MSCR_PH10),
S32V_PINCTRL_PIN(S32V234_MSCR_PH11),
S32V_PINCTRL_PIN(S32V234_MSCR_PH12),
S32V_PINCTRL_PIN(S32V234_MSCR_PH13),
S32V_PINCTRL_PIN(S32V234_MSCR_PH14),
S32V_PINCTRL_PIN(S32V234_MSCR_PH15),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ0),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ1),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ2),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ3),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ4),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ5),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ6),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ7),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ8),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ9),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ10),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ11),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ12),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ13),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ14),
S32V_PINCTRL_PIN(S32V234_MSCR_PJ15),
S32V_PINCTRL_PIN(S32V234_MSCR_PK0),
S32V_PINCTRL_PIN(S32V234_MSCR_PK1),
S32V_PINCTRL_PIN(S32V234_MSCR_PK2),
S32V_PINCTRL_PIN(S32V234_MSCR_PK3),
S32V_PINCTRL_PIN(S32V234_MSCR_PK4),
S32V_PINCTRL_PIN(S32V234_MSCR_PK5),
S32V_PINCTRL_PIN(S32V234_MSCR_PK6),
S32V_PINCTRL_PIN(S32V234_MSCR_PK7),
S32V_PINCTRL_PIN(S32V234_MSCR_PK8),
S32V_PINCTRL_PIN(S32V234_MSCR_PK9),
S32V_PINCTRL_PIN(S32V234_MSCR_PK10),
S32V_PINCTRL_PIN(S32V234_MSCR_PK11),
S32V_PINCTRL_PIN(S32V234_MSCR_PK12),
S32V_PINCTRL_PIN(S32V234_MSCR_PK13),
S32V_PINCTRL_PIN(S32V234_MSCR_PK14),
S32V_PINCTRL_PIN(S32V234_MSCR_PK15),
S32V_PINCTRL_PIN(S32V234_MSCR_PL0),
S32V_PINCTRL_PIN(S32V234_MSCR_PL1),
S32V_PINCTRL_PIN(S32V234_MSCR_PL2),
S32V_PINCTRL_PIN(S32V234_MSCR_PL3),
S32V_PINCTRL_PIN(S32V234_MSCR_PL4),
S32V_PINCTRL_PIN(S32V234_MSCR_PL5),
S32V_PINCTRL_PIN(S32V234_MSCR_PL8),
};
static struct s32v_pinctrl_soc_info s32v234_pinctrl_info = {
.pins = s32v234_pinctrl_pads,
.npins = ARRAY_SIZE(s32v234_pinctrl_pads),
};
static const struct of_device_id s32v234_pinctrl_of_match[] = {
{ .compatible = "fsl,s32v234-siul2", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, s32v234_pinctrl_of_match);
static int s32v234_pinctrl_probe(struct platform_device *pdev)
{
return s32v_pinctrl_probe(pdev, &s32v234_pinctrl_info);
}
static struct platform_driver s32v234_pinctrl_driver = {
.driver = {
.name = "s32v234-siul2",
.owner = THIS_MODULE,
.of_match_table = s32v234_pinctrl_of_match,
},
.probe = s32v234_pinctrl_probe,
.remove = s32v_pinctrl_remove,
};
module_platform_driver(s32v234_pinctrl_driver);
MODULE_DESCRIPTION("Freescale S32V234 pinctrl driver");
MODULE_LICENSE("GPL v2");
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