![Jiri Slaby](/assets/img/avatar_default.png)
There is code duplicated over all architecture's headers for futex_atomic_op_inuser. Namely op decoding, access_ok check for uaddr, and comparison of the result. Remove this duplication and leave up to the arches only the needed assembly which is now in arch_futex_atomic_op_inuser. This effectively distributes the Will Deacon's arm64 fix for undefined behaviour reported by UBSAN to all architectures. The fix was done in commit5f16a046f8
(arm64: futex: Fix undefined behaviour with FUTEX_OP_OPARG_SHIFT usage). Look there for an example dump. And as suggested by Thomas, check for negative oparg too, because it was also reported to cause undefined behaviour report. Note that s390 removed access_ok check ind12a29703
("s390/uaccess: remove pointless access_ok() checks") as access_ok there returns true. We introduce it back to the helper for the sake of simplicity (it gets optimized away anyway). Signed-off-by: Jiri Slaby <jslaby@suse.cz> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> [s390] Acked-by: Chris Metcalf <cmetcalf@mellanox.com> [for tile] Reviewed-by: Darren Hart (VMware) <dvhart@infradead.org> Reviewed-by: Will Deacon <will.deacon@arm.com> [core/arm64] Cc: linux-mips@linux-mips.org Cc: Rich Felker <dalias@libc.org> Cc: linux-ia64@vger.kernel.org Cc: linux-sh@vger.kernel.org Cc: peterz@infradead.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Paul Mackerras <paulus@samba.org> Cc: sparclinux@vger.kernel.org Cc: Jonas Bonn <jonas@southpole.se> Cc: linux-s390@vger.kernel.org Cc: linux-arch@vger.kernel.org Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: linux-hexagon@vger.kernel.org Cc: Helge Deller <deller@gmx.de> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Matt Turner <mattst88@gmail.com> Cc: linux-snps-arc@lists.infradead.org Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-xtensa@linux-xtensa.org Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Cc: openrisc@lists.librecores.org Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Stafford Horne <shorne@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Richard Henderson <rth@twiddle.net> Cc: Chris Zankel <chris@zankel.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-parisc@vger.kernel.org Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Richard Kuo <rkuo@codeaurora.org> Cc: linux-alpha@vger.kernel.org Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: linuxppc-dev@lists.ozlabs.org Cc: "David S. Miller" <davem@davemloft.net> Link: http://lkml.kernel.org/r/20170824073105.3901-1-jslaby@suse.cz
224 lines
5.9 KiB
C
224 lines
5.9 KiB
C
/* futex.c: futex operations
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*
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* Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/futex.h>
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#include <asm/errno.h>
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/*
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* the various futex operations; MMU fault checking is ignored under no-MMU
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* conditions
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*/
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static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr, int *_oldval)
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{
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int oldval, ret;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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"1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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"2: cst.p %3,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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" setlos 0,%2 \n"
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"3: \n"
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".subsection 2 \n"
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"4: setlos %5,%2 \n"
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" bra 3b \n"
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".previous \n"
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".section __ex_table,\"a\" \n"
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" .balign 8 \n"
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" .long 1b,4b \n"
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" .long 2b,4b \n"
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".previous"
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: "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
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: "3"(oparg), "i"(-EFAULT)
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: "memory", "cc7", "cc3", "icc3"
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);
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*_oldval = oldval;
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return ret;
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}
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static inline int atomic_futex_op_xchg_add(int oparg, u32 __user *uaddr, int *_oldval)
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{
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int oldval, ret;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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"1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" add %1,%3,%3 \n"
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"2: cst.p %3,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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" setlos 0,%2 \n"
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"3: \n"
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".subsection 2 \n"
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"4: setlos %5,%2 \n"
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" bra 3b \n"
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".previous \n"
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".section __ex_table,\"a\" \n"
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" .balign 8 \n"
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" .long 1b,4b \n"
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" .long 2b,4b \n"
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".previous"
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: "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
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: "3"(oparg), "i"(-EFAULT)
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: "memory", "cc7", "cc3", "icc3"
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);
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*_oldval = oldval;
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return ret;
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}
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static inline int atomic_futex_op_xchg_or(int oparg, u32 __user *uaddr, int *_oldval)
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{
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int oldval, ret;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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"1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" or %1,%3,%3 \n"
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"2: cst.p %3,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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" setlos 0,%2 \n"
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"3: \n"
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".subsection 2 \n"
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"4: setlos %5,%2 \n"
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" bra 3b \n"
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".previous \n"
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".section __ex_table,\"a\" \n"
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" .balign 8 \n"
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" .long 1b,4b \n"
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" .long 2b,4b \n"
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".previous"
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: "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
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: "3"(oparg), "i"(-EFAULT)
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: "memory", "cc7", "cc3", "icc3"
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);
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*_oldval = oldval;
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return ret;
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}
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static inline int atomic_futex_op_xchg_and(int oparg, u32 __user *uaddr, int *_oldval)
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{
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int oldval, ret;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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"1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" and %1,%3,%3 \n"
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"2: cst.p %3,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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" setlos 0,%2 \n"
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"3: \n"
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".subsection 2 \n"
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"4: setlos %5,%2 \n"
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" bra 3b \n"
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".previous \n"
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".section __ex_table,\"a\" \n"
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" .balign 8 \n"
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" .long 1b,4b \n"
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" .long 2b,4b \n"
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".previous"
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: "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
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: "3"(oparg), "i"(-EFAULT)
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: "memory", "cc7", "cc3", "icc3"
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);
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*_oldval = oldval;
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return ret;
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}
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static inline int atomic_futex_op_xchg_xor(int oparg, u32 __user *uaddr, int *_oldval)
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{
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int oldval, ret;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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"1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" xor %1,%3,%3 \n"
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"2: cst.p %3,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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" setlos 0,%2 \n"
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"3: \n"
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".subsection 2 \n"
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"4: setlos %5,%2 \n"
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" bra 3b \n"
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".previous \n"
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".section __ex_table,\"a\" \n"
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" .balign 8 \n"
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" .long 1b,4b \n"
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" .long 2b,4b \n"
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".previous"
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: "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
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: "3"(oparg), "i"(-EFAULT)
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: "memory", "cc7", "cc3", "icc3"
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);
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*_oldval = oldval;
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return ret;
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}
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/*****************************************************************************/
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/*
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* do the futex operations
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*/
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int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
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break;
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case FUTEX_OP_ADD:
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ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
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break;
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case FUTEX_OP_OR:
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ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
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break;
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case FUTEX_OP_ANDN:
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ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
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break;
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case FUTEX_OP_XOR:
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ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
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break;
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default:
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ret = -ENOSYS;
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break;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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} /* end arch_futex_atomic_op_inuser() */
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