![Haojian Zhuang](/assets/img/avatar_default.png)
In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
495 lines
18 KiB
C
495 lines
18 KiB
C
/*
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* linux/include/linux/clk-provider.h
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*
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* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_CLK_PROVIDER_H
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#define __LINUX_CLK_PROVIDER_H
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#include <linux/clk.h>
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#ifdef CONFIG_COMMON_CLK
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/*
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* flags used across common struct clk. these flags should only affect the
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* top-level framework. custom flags for dealing with hardware specifics
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* belong in struct clk_foo
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*/
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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struct clk_hw;
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/**
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* struct clk_ops - Callback operations for hardware clocks; these are to
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* be provided by the clock implementation, and will be called by drivers
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* through the clk_* api.
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*
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* @prepare: Prepare the clock for enabling. This must not return until
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* the clock is fully prepared, and it's safe to call clk_enable.
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* This callback is intended to allow clock implementations to
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* do any initialisation that may sleep. Called with
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* prepare_lock held.
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*
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* @unprepare: Release the clock from its prepared state. This will typically
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* undo any work done in the @prepare callback. Called with
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* prepare_lock held.
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*
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* @is_prepared: Queries the hardware to determine if the clock is prepared.
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* This function is allowed to sleep. Optional, if this op is not
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* set then the prepare count will be used.
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*
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* @unprepare_unused: Unprepare the clock atomically. Only called from
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* clk_disable_unused for prepare clocks with special needs.
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* Called with prepare mutex held. This function may sleep.
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*
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* @enable: Enable the clock atomically. This must not return until the
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* clock is generating a valid clock signal, usable by consumer
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* devices. Called with enable_lock held. This function must not
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* sleep.
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*
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* @disable: Disable the clock atomically. Called with enable_lock held.
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* This function must not sleep.
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*
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* @is_enabled: Queries the hardware to determine if the clock is enabled.
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* This function must not sleep. Optional, if this op is not
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* set then the enable count will be used.
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*
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* @disable_unused: Disable the clock atomically. Only called from
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* clk_disable_unused for gate clocks with special needs.
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* Called with enable_lock held. This function must not
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* sleep.
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*
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* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
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* parent rate is an input parameter. It is up to the caller to
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* ensure that the prepare_mutex is held across this call.
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* Returns the calculated rate. Optional, but recommended - if
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* this op is not set then clock rate will be initialized to 0.
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*
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* @round_rate: Given a target rate as input, returns the closest rate actually
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* supported by the clock.
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*
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* @get_parent: Queries the hardware to determine the parent of a clock. The
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* return value is a u8 which specifies the index corresponding to
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* the parent clock. This index can be applied to either the
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* .parent_names or .parents arrays. In short, this function
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* translates the parent value read from hardware into an array
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* index. Currently only called when the clock is initialized by
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* __clk_init. This callback is mandatory for clocks with
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* multiple parents. It is optional (and unnecessary) for clocks
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* with 0 or 1 parents.
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*
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* @set_parent: Change the input source of this clock; for clocks with multiple
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* possible parents specify a new parent by passing in the index
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* as a u8 corresponding to the parent in either the .parent_names
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* or .parents arrays. This function in affect translates an
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* array index into the value programmed into the hardware.
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* Returns 0 on success, -EERROR otherwise.
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*
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* @set_rate: Change the rate of this clock. The requested rate is specified
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* by the second argument, which should typically be the return
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* of .round_rate call. The third argument gives the parent rate
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* which is likely helpful for most .set_rate implementation.
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* Returns 0 on success, -EERROR otherwise.
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*
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* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
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* implementations to split any work between atomic (enable) and sleepable
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* (prepare) contexts. If enabling a clock requires code that might sleep,
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* this must be done in clk_prepare. Clock enable code that will never be
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* called in a sleepable context may be implemented in clk_enable.
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*
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* Typically, drivers will call clk_prepare when a clock may be needed later
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* (eg. when a device is opened), and clk_enable when the clock is actually
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* required (eg. from an interrupt). Note that clk_prepare MUST have been
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* called before clk_enable.
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*/
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struct clk_ops {
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int (*prepare)(struct clk_hw *hw);
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void (*unprepare)(struct clk_hw *hw);
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int (*is_prepared)(struct clk_hw *hw);
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void (*unprepare_unused)(struct clk_hw *hw);
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int (*enable)(struct clk_hw *hw);
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void (*disable)(struct clk_hw *hw);
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int (*is_enabled)(struct clk_hw *hw);
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void (*disable_unused)(struct clk_hw *hw);
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unsigned long (*recalc_rate)(struct clk_hw *hw,
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unsigned long parent_rate);
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long (*round_rate)(struct clk_hw *hw, unsigned long,
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unsigned long *);
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int (*set_parent)(struct clk_hw *hw, u8 index);
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u8 (*get_parent)(struct clk_hw *hw);
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int (*set_rate)(struct clk_hw *hw, unsigned long,
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unsigned long);
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void (*init)(struct clk_hw *hw);
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};
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/**
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* struct clk_init_data - holds init data that's common to all clocks and is
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* shared between the clock provider and the common clock framework.
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*
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* @name: clock name
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* @ops: operations this clock supports
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* @parent_names: array of string names for all possible parents
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* @num_parents: number of possible parents
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* @flags: framework-level hints and quirks
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*/
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struct clk_init_data {
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const char *name;
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const struct clk_ops *ops;
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const char **parent_names;
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u8 num_parents;
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unsigned long flags;
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};
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/**
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* struct clk_hw - handle for traversing from a struct clk to its corresponding
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* hardware-specific structure. struct clk_hw should be declared within struct
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* clk_foo and then referenced by the struct clk instance that uses struct
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* clk_foo's clk_ops
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*
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* @clk: pointer to the struct clk instance that points back to this struct
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* clk_hw instance
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*
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* @init: pointer to struct clk_init_data that contains the init data shared
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* with the common clock framework.
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*/
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struct clk_hw {
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struct clk *clk;
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const struct clk_init_data *init;
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};
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/*
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* DOC: Basic clock implementations common to many platforms
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*
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* Each basic clock hardware type is comprised of a structure describing the
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* clock hardware, implementations of the relevant callbacks in struct clk_ops,
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* unique flags for that hardware type, a registration function and an
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* alternative macro for static initialization
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*/
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/**
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* struct clk_fixed_rate - fixed-rate clock
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* @hw: handle between common and hardware-specific interfaces
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* @fixed_rate: constant frequency of clock
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*/
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struct clk_fixed_rate {
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struct clk_hw hw;
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unsigned long fixed_rate;
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u8 flags;
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};
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extern const struct clk_ops clk_fixed_rate_ops;
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struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned long fixed_rate);
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void of_fixed_clk_setup(struct device_node *np);
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/**
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* struct clk_gate - gating clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling gate
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* @bit_idx: single bit controlling gate
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Clock which can gate its output. Implements .enable & .disable
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*
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* Flags:
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* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
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* enable the clock. Setting this flag does the opposite: setting the bit
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* disable the clock and clearing it enables the clock
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* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
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* of this register, and mask of gate bits are in higher 16-bit of this
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* register. While setting the gate bits, higher 16-bit should also be
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* updated to indicate changing gate bits.
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*/
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struct clk_gate {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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u8 flags;
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spinlock_t *lock;
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};
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#define CLK_GATE_SET_TO_DISABLE BIT(0)
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#define CLK_GATE_HIWORD_MASK BIT(1)
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extern const struct clk_ops clk_gate_ops;
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struct clk *clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock);
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struct clk_div_table {
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unsigned int val;
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unsigned int div;
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};
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/**
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* struct clk_divider - adjustable divider clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register containing the divider
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* @shift: shift to the divider bit field
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* @width: width of the divider bit field
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* @table: array of value/divider pairs, last entry should have div = 0
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* @lock: register lock
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*
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* Clock with an adjustable divider affecting its output frequency. Implements
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* .recalc_rate, .set_rate and .round_rate
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*
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* Flags:
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* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
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* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
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* the raw value read from the register, with the value of zero considered
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* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
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* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
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* the hardware register
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* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
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* CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
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* Some hardware implementations gracefully handle this case and allow a
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* zero divisor by not modifying their input clock
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* (divide by one / bypass).
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* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
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* of this register, and mask of divider bits are in higher 16-bit of this
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* register. While setting the divider bits, higher 16-bit should also be
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* updated to indicate changing divider bits.
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*/
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struct clk_divider {
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struct clk_hw hw;
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void __iomem *reg;
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u8 shift;
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u8 width;
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u8 flags;
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const struct clk_div_table *table;
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spinlock_t *lock;
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};
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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extern const struct clk_ops clk_divider_ops;
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock);
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struct clk *clk_register_divider_table(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock);
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/**
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* struct clk_mux - multiplexer clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling multiplexer
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* @shift: shift to multiplexer bit field
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* @width: width of mutliplexer bit field
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Clock with multiple selectable parents. Implements .get_parent, .set_parent
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* and .recalc_rate
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*
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* Flags:
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* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
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* CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
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* CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
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* register, and mask of mux bits are in higher 16-bit of this register.
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* While setting the mux bits, higher 16-bit should also be updated to
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* indicate changing mux bits.
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*/
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struct clk_mux {
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struct clk_hw hw;
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void __iomem *reg;
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u32 *table;
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u32 mask;
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u8 shift;
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u8 flags;
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spinlock_t *lock;
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};
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#define CLK_MUX_INDEX_ONE BIT(0)
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#define CLK_MUX_INDEX_BIT BIT(1)
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#define CLK_MUX_HIWORD_MASK BIT(2)
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extern const struct clk_ops clk_mux_ops;
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock);
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock);
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void of_fixed_factor_clk_setup(struct device_node *node);
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/**
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* struct clk_fixed_factor - fixed multiplier and divider clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @mult: multiplier
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* @div: divider
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*
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* Clock with a fixed multiplier and divider. The output frequency is the
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* parent clock rate divided by div and multiplied by mult.
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* Implements .recalc_rate, .set_rate and .round_rate
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*/
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struct clk_fixed_factor {
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struct clk_hw hw;
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unsigned int mult;
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unsigned int div;
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};
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extern struct clk_ops clk_fixed_factor_ops;
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struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div);
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/***
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* struct clk_composite - aggregate clock of mux, divider and gate clocks
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*
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* @hw: handle between common and hardware-specific interfaces
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* @mux_hw: handle between composite and hardware-specific mux clock
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* @rate_hw: handle between composite and hardware-specific rate clock
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* @gate_hw: handle between composite and hardware-specific gate clock
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* @mux_ops: clock ops for mux
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* @rate_ops: clock ops for rate
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* @gate_ops: clock ops for gate
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*/
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struct clk_composite {
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struct clk_hw hw;
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struct clk_ops ops;
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struct clk_hw *mux_hw;
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struct clk_hw *rate_hw;
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struct clk_hw *gate_hw;
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const struct clk_ops *mux_ops;
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const struct clk_ops *rate_ops;
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const struct clk_ops *gate_ops;
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};
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struct clk *clk_register_composite(struct device *dev, const char *name,
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const char **parent_names, int num_parents,
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struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
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struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
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struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
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unsigned long flags);
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/**
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* clk_register - allocate a new clock, register it and return an opaque cookie
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* @dev: device that is registering this clock
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* @hw: link to hardware-specific clock data
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*
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* clk_register is the primary interface for populating the clock tree with new
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* clock nodes. It returns a pointer to the newly allocated struct clk which
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* cannot be dereferenced by driver code but may be used in conjuction with the
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* rest of the clock API. In the event of an error clk_register will return an
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* error code; drivers must test for an error code after calling clk_register.
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*/
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struct clk *clk_register(struct device *dev, struct clk_hw *hw);
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struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
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void clk_unregister(struct clk *clk);
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void devm_clk_unregister(struct device *dev, struct clk *clk);
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/* helper functions */
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const char *__clk_get_name(struct clk *clk);
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struct clk_hw *__clk_get_hw(struct clk *clk);
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u8 __clk_get_num_parents(struct clk *clk);
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struct clk *__clk_get_parent(struct clk *clk);
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unsigned int __clk_get_enable_count(struct clk *clk);
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unsigned int __clk_get_prepare_count(struct clk *clk);
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unsigned long __clk_get_rate(struct clk *clk);
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unsigned long __clk_get_flags(struct clk *clk);
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bool __clk_is_prepared(struct clk *clk);
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bool __clk_is_enabled(struct clk *clk);
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struct clk *__clk_lookup(const char *name);
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/*
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* FIXME clock api without lock protection
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*/
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int __clk_prepare(struct clk *clk);
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void __clk_unprepare(struct clk *clk);
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void __clk_reparent(struct clk *clk, struct clk *new_parent);
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unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
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struct of_device_id;
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typedef void (*of_clk_init_cb_t)(struct device_node *);
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struct clk_onecell_data {
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struct clk **clks;
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unsigned int clk_num;
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};
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#define CLK_OF_DECLARE(name, compat, fn) \
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static const struct of_device_id __clk_of_table_##name \
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__used __section(__clk_of_table) \
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= { .compatible = compat, .data = fn };
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#ifdef CONFIG_OF
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int of_clk_add_provider(struct device_node *np,
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struct clk *(*clk_src_get)(struct of_phandle_args *args,
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void *data),
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void *data);
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void of_clk_del_provider(struct device_node *np);
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struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
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void *data);
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struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
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const char *of_clk_get_parent_name(struct device_node *np, int index);
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void of_clk_init(const struct of_device_id *matches);
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#else /* !CONFIG_OF */
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static inline int of_clk_add_provider(struct device_node *np,
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struct clk *(*clk_src_get)(struct of_phandle_args *args,
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void *data),
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void *data)
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{
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return 0;
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}
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#define of_clk_del_provider(np) \
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{ while (0); }
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static inline struct clk *of_clk_src_simple_get(
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struct of_phandle_args *clkspec, void *data)
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{
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return ERR_PTR(-ENOENT);
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}
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static inline struct clk *of_clk_src_onecell_get(
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struct of_phandle_args *clkspec, void *data)
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{
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return ERR_PTR(-ENOENT);
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}
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static inline const char *of_clk_get_parent_name(struct device_node *np,
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int index)
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{
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return NULL;
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}
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#define of_clk_init(matches) \
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{ while (0); }
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#endif /* CONFIG_OF */
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#endif /* CONFIG_COMMON_CLK */
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#endif /* CLK_PROVIDER_H */
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