alistair23-linux/arch/arm/boot/dts/exynos5410.dtsi

/*
 * SAMSUNG EXYNOS5410 SoC device tree source
 *
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
 * EXYNOS5410 based board files can include this file and provide
 * values for board specfic bindings.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "exynos54xx.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos5410.h>

/ {
	compatible = "samsung,exynos5410", "samsung,exynos5";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			clock-frequency = <1600000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			clock-frequency = <1600000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x2>;
			clock-frequency = <1600000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x3>;
			clock-frequency = <1600000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pmu_system_controller: system-controller@10040000 {
			compatible = "samsung,exynos5410-pmu", "syscon";
			reg = <0x10040000 0x5000>;
			clock-names = "clkout16";
			clocks = <&fin_pll>;
			#clock-cells = <1>;
		};

		clock: clock-controller@10010000 {
			compatible = "samsung,exynos5410-clock";
			reg = <0x10010000 0x30000>;
			#clock-cells = <1>;
		};

		mmc_0: mmc@12200000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12200000 0x1000>;
			interrupts = <0 75 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			status = "disabled";
		};

		mmc_1: mmc@12210000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12210000 0x1000>;
			interrupts = <0 76 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			status = "disabled";
		};

		mmc_2: mmc@12220000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12220000 0x1000>;
			interrupts = <0 77 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			status = "disabled";
		};

		pinctrl_0: pinctrl@13400000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x13400000 0x1000>;
			interrupts = <0 45 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <0 32 0>;
			};
		};

		pinctrl_1: pinctrl@14000000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x14000000 0x1000>;
			interrupts = <0 46 0>;
		};

		pinctrl_2: pinctrl@10d10000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x10d10000 0x1000>;
			interrupts = <0 50 0>;
		};

		pinctrl_3: pinctrl@03860000 {
			compatible = "samsung,exynos5410-pinctrl";
			reg = <0x03860000 0x1000>;
			interrupts = <0 47 0>;
		};
	};
};

&mct {
	clocks = <&fin_pll>, <&clock CLK_MCT>;
	clock-names = "fin_pll", "mct";
};

&pwm {
	clocks = <&clock CLK_PWM>;
	clock-names = "timers";
};

&serial_0 {
	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
	clock-names = "uart", "clk_uart_baud0";
};

&serial_1 {
	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
	clock-names = "uart", "clk_uart_baud0";
};

&serial_2 {
	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
	clock-names = "uart", "clk_uart_baud0";
};

&serial_3 {
	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
	clock-names = "uart", "clk_uart_baud0";
};

&sromc {
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x04000000 0x20000
		  1 0 0x05000000 0x20000
		  2 0 0x06000000 0x20000
		  3 0 0x07000000 0x20000>;
};

&usbdrd3_0 {
	clocks = <&clock CLK_USBD300>;
	clock-names = "usbdrd30";
};

&usbdrd_phy0 {
	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
	clock-names = "phy", "ref";
	samsung,pmu-syscon = <&pmu_system_controller>;
};

&usbdrd3_1 {
	clocks = <&clock CLK_USBD301>;
	clock-names = "usbdrd30";
};

&usbdrd_phy1 {
	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
	clock-names = "phy", "ref";
	samsung,pmu-syscon = <&pmu_system_controller>;
};

&usbhost1 {
	clocks = <&clock CLK_USBH20>;
	clock-names = "usbhost";
};

&usbhost2 {
	clocks = <&clock CLK_USBH20>;
	clock-names = "usbhost";
};

&usb2_phy {
	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
	clock-names = "phy", "ref";
	samsung,sysreg-phandle = <&sysreg_system_controller>;
	samsung,pmureg-phandle = <&pmu_system_controller>;
};

#include "exynos5410-pinctrl.dtsi"