![Bjorn Helgaas](/assets/img/avatar_default.png)
amd_irongate_configure(), ati_configure(), and nvidia_configure() call ioremap() on an address read directly from a BAR. But a BAR contains a bus address, and ioremap() expects a CPU physical address. Use pci_resource_start() to obtain the physical address. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
567 lines
15 KiB
C
567 lines
15 KiB
C
/*
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* AMD K7 AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <linux/page-flags.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include "agp.h"
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#define AMD_MMBASE_BAR 1
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#define AMD_APSIZE 0xac
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#define AMD_MODECNTL 0xb0
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#define AMD_MODECNTL2 0xb2
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#define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
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#define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
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#define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
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#define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
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static struct pci_device_id agp_amdk7_pci_table[];
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struct amd_page_map {
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unsigned long *real;
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unsigned long __iomem *remapped;
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};
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static struct _amd_irongate_private {
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volatile u8 __iomem *registers;
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struct amd_page_map **gatt_pages;
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int num_tables;
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} amd_irongate_private;
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static int amd_create_page_map(struct amd_page_map *page_map)
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{
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int i;
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page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
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if (page_map->real == NULL)
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return -ENOMEM;
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set_memory_uc((unsigned long)page_map->real, 1);
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page_map->remapped = page_map->real;
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for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
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writel(agp_bridge->scratch_page, page_map->remapped+i);
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readl(page_map->remapped+i); /* PCI Posting. */
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}
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return 0;
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}
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static void amd_free_page_map(struct amd_page_map *page_map)
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{
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set_memory_wb((unsigned long)page_map->real, 1);
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free_page((unsigned long) page_map->real);
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}
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static void amd_free_gatt_pages(void)
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{
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int i;
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struct amd_page_map **tables;
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struct amd_page_map *entry;
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tables = amd_irongate_private.gatt_pages;
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for (i = 0; i < amd_irongate_private.num_tables; i++) {
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entry = tables[i];
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if (entry != NULL) {
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if (entry->real != NULL)
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amd_free_page_map(entry);
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kfree(entry);
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}
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}
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kfree(tables);
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amd_irongate_private.gatt_pages = NULL;
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}
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static int amd_create_gatt_pages(int nr_tables)
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{
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struct amd_page_map **tables;
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struct amd_page_map *entry;
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int retval = 0;
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int i;
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tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
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if (tables == NULL)
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return -ENOMEM;
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for (i = 0; i < nr_tables; i++) {
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entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
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tables[i] = entry;
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if (entry == NULL) {
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retval = -ENOMEM;
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break;
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}
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retval = amd_create_page_map(entry);
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if (retval != 0)
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break;
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}
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amd_irongate_private.num_tables = i;
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amd_irongate_private.gatt_pages = tables;
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if (retval != 0)
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amd_free_gatt_pages();
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return retval;
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}
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/* Since we don't need contiguous memory we just try
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* to get the gatt table once
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*/
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#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
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#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
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GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
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#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
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#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
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GET_PAGE_DIR_IDX(addr)]->remapped)
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static int amd_create_gatt_table(struct agp_bridge_data *bridge)
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{
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struct aper_size_info_lvl2 *value;
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struct amd_page_map page_dir;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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int retval;
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int i;
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value = A_SIZE_LVL2(agp_bridge->current_size);
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retval = amd_create_page_map(&page_dir);
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if (retval != 0)
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return retval;
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retval = amd_create_gatt_pages(value->num_entries / 1024);
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if (retval != 0) {
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amd_free_page_map(&page_dir);
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return retval;
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}
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agp_bridge->gatt_table_real = (u32 *)page_dir.real;
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agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
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agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
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/* Get the address for the gart region.
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* This is a bus address even on the alpha, b/c its
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* used to program the agp master not the cpu
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*/
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addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
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agp_bridge->gart_bus_addr = addr;
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/* Calculate the agp offset */
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for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
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writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
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page_dir.remapped+GET_PAGE_DIR_OFF(addr));
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readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
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}
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for (i = 0; i < value->num_entries; i++) {
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addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
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readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
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}
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return 0;
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}
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static int amd_free_gatt_table(struct agp_bridge_data *bridge)
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{
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struct amd_page_map page_dir;
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page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
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page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
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amd_free_gatt_pages();
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amd_free_page_map(&page_dir);
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return 0;
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}
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static int amd_irongate_fetch_size(void)
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{
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int i;
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u32 temp;
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struct aper_size_info_lvl2 *values;
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pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
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temp = (temp & 0x0000000e);
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values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int amd_irongate_configure(void)
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{
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struct aper_size_info_lvl2 *current_size;
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phys_addr_t reg;
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u32 temp;
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u16 enable_reg;
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current_size = A_SIZE_LVL2(agp_bridge->current_size);
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if (!amd_irongate_private.registers) {
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/* Get the memory mapped registers */
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reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
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amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
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if (!amd_irongate_private.registers)
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return -ENOMEM;
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}
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/* Write out the address of the gatt table */
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writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
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readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
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/* Write the Sync register */
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pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
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/* Set indexing mode */
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pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
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/* Write the enable register */
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enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
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enable_reg = (enable_reg | 0x0004);
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writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
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readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
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/* Write out the size register */
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pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
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temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
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pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
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/* Flush the tlb */
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writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
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readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
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return 0;
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}
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static void amd_irongate_cleanup(void)
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{
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struct aper_size_info_lvl2 *previous_size;
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u32 temp;
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u16 enable_reg;
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previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
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enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
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enable_reg = (enable_reg & ~(0x0004));
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writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
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readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
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/* Write back the previous size and disable gart translation */
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pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
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temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
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pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
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iounmap((void __iomem *) amd_irongate_private.registers);
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}
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/*
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* This routine could be implemented by taking the addresses
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* written to the GATT, and flushing them individually. However
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* currently it just flushes the whole table. Which is probably
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* more efficient, since agp_memory blocks can be a large number of
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* entries.
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*/
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static void amd_irongate_tlbflush(struct agp_memory *temp)
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{
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writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
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readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
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}
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static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i, j, num_entries;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
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if (type != mem->type ||
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agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
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return -EINVAL;
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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j = pg_start;
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while (j < (pg_start + mem->page_count)) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
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return -EBUSY;
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j++;
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}
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if (!mem->is_flushed) {
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global_cache_flush();
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mem->is_flushed = true;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_generic_mask_memory(agp_bridge,
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page_to_phys(mem->pages[i]),
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mem->type),
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cur_gatt+GET_GATT_OFF(addr));
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readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
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}
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amd_irongate_tlbflush(mem);
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return 0;
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}
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static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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if (type != mem->type ||
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agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
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return -EINVAL;
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
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readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
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}
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amd_irongate_tlbflush(mem);
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return 0;
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}
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static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
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{
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{2048, 524288, 0x0000000c},
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{1024, 262144, 0x0000000a},
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{512, 131072, 0x00000008},
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{256, 65536, 0x00000006},
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{128, 32768, 0x00000004},
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{64, 16384, 0x00000002},
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{32, 8192, 0x00000000}
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};
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static const struct gatt_mask amd_irongate_masks[] =
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{
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{.mask = 1, .type = 0}
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};
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static const struct agp_bridge_driver amd_irongate_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = amd_irongate_sizes,
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.size_type = LVL2_APER_SIZE,
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.num_aperture_sizes = 7,
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.needs_scratch_page = true,
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.configure = amd_irongate_configure,
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.fetch_size = amd_irongate_fetch_size,
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.cleanup = amd_irongate_cleanup,
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.tlb_flush = amd_irongate_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = amd_irongate_masks,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = amd_create_gatt_table,
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.free_gatt_table = amd_free_gatt_table,
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.insert_memory = amd_insert_memory,
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.remove_memory = amd_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static struct agp_device_ids amd_agp_device_ids[] =
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{
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{
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.device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
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.chipset_name = "Irongate",
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},
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{
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.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
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.chipset_name = "761",
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},
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{
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.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
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.chipset_name = "760MP",
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},
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{ }, /* dummy final entry, always present */
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};
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static int agp_amdk7_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_bridge_data *bridge;
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u8 cap_ptr;
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int j;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return -ENODEV;
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j = ent - agp_amdk7_pci_table;
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dev_info(&pdev->dev, "AMD %s chipset\n",
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amd_agp_device_ids[j].chipset_name);
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->driver = &amd_irongate_driver;
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bridge->dev_private_data = &amd_irongate_private,
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bridge->dev = pdev;
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bridge->capndx = cap_ptr;
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/* 751 Errata (22564_B-1.PDF)
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erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
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system controller may experience noise due to strong drive strengths
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*/
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if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
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struct pci_dev *gfxcard=NULL;
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cap_ptr = 0;
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while (!cap_ptr) {
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gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
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if (!gfxcard) {
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dev_info(&pdev->dev, "no AGP VGA controller\n");
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return -ENODEV;
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}
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cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
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}
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/* With so many variants of NVidia cards, it's simpler just
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to blacklist them all, and then whitelist them as needed
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(if necessary at all). */
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if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
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agp_bridge->flags |= AGP_ERRATA_1X;
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dev_info(&pdev->dev, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
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}
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pci_dev_put(gfxcard);
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}
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/* 761 Errata (23613_F.pdf)
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* Revisions B0/B1 were a disaster.
|
|
* erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
|
|
* erratum 45: Timing problem prevents fast writes -- Disable fast write.
|
|
* erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
|
|
* With this lot disabled, we should prevent lockups. */
|
|
if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
|
|
if (pdev->revision == 0x10 || pdev->revision == 0x11) {
|
|
agp_bridge->flags = AGP_ERRATA_FASTWRITES;
|
|
agp_bridge->flags |= AGP_ERRATA_SBA;
|
|
agp_bridge->flags |= AGP_ERRATA_1X;
|
|
dev_info(&pdev->dev, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
|
|
}
|
|
}
|
|
|
|
/* Fill in the mode register */
|
|
pci_read_config_dword(pdev,
|
|
bridge->capndx+PCI_AGP_STATUS,
|
|
&bridge->mode);
|
|
|
|
pci_set_drvdata(pdev, bridge);
|
|
return agp_add_bridge(bridge);
|
|
}
|
|
|
|
static void agp_amdk7_remove(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
agp_remove_bridge(bridge);
|
|
agp_put_bridge(bridge);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int agp_amdk7_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
pci_save_state(pdev);
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int agp_amdk7_resume(struct pci_dev *pdev)
|
|
{
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
|
|
return amd_irongate_driver.configure();
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
/* must be the same order as name table above */
|
|
static struct pci_device_id agp_amdk7_pci_table[] = {
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
|
|
|
|
static struct pci_driver agp_amdk7_pci_driver = {
|
|
.name = "agpgart-amdk7",
|
|
.id_table = agp_amdk7_pci_table,
|
|
.probe = agp_amdk7_probe,
|
|
.remove = agp_amdk7_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = agp_amdk7_suspend,
|
|
.resume = agp_amdk7_resume,
|
|
#endif
|
|
};
|
|
|
|
static int __init agp_amdk7_init(void)
|
|
{
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
return pci_register_driver(&agp_amdk7_pci_driver);
|
|
}
|
|
|
|
static void __exit agp_amdk7_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&agp_amdk7_pci_driver);
|
|
}
|
|
|
|
module_init(agp_amdk7_init);
|
|
module_exit(agp_amdk7_cleanup);
|
|
|
|
MODULE_LICENSE("GPL and additional rights");
|