2c80661d2e
The drivers current default configuration drives the pixel data on rising edge of the pixel clock. However, most display sample data on rising edge... This leads to color shift artefacts visible especially at edges. This patch changes the relevant defines to be useful and actually set the bits, and changes pixel clock polarity to drive the pixel data on falling edge by default. The patch also adds an explicit pixel clock polarity flag to the display introduced with the driver (NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to retain the initial behavior. Signed-off-by: Stefan Agner <stefan@agner.ch> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| fsl_dcu_drm_crtc.c | ||
| fsl_dcu_drm_crtc.h | ||
| fsl_dcu_drm_drv.c | ||
| fsl_dcu_drm_drv.h | ||
| fsl_dcu_drm_fbdev.c | ||
| fsl_dcu_drm_kms.c | ||
| fsl_dcu_drm_output.h | ||
| fsl_dcu_drm_plane.c | ||
| fsl_dcu_drm_plane.h | ||
| fsl_dcu_drm_rgb.c | ||
| fsl_tcon.c | ||
| fsl_tcon.h | ||