6e08d6bbeb
This driver supports the pin/GPIO controllers found in newer Intel SoCs like Cherryview and Braswell. The driver provides full GPIO support and minimal set of pin controlling funtionality. The driver is based on the original Cherryview GPIO driver authored by Ning Li and Alan Cox. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
28 lines
805 B
Plaintext
28 lines
805 B
Plaintext
#
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# Intel pin control drivers
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#
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config PINCTRL_BAYTRAIL
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bool "Intel Baytrail GPIO pin control"
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depends on GPIOLIB && ACPI
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select GPIOLIB_IRQCHIP
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help
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driver for memory mapped GPIO functionality on Intel Baytrail
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platforms. Supports 3 banks with 102, 28 and 44 gpios.
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Most pins are usually muxed to some other functionality by firmware,
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so only a small amount is available for gpio use.
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Requires ACPI device enumeration code to set up a platform device.
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config PINCTRL_CHERRYVIEW
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tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
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depends on ACPI
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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help
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Cherryview/Braswell pinctrl driver provides an interface that
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allows configuring of SoC pins and using them as GPIOs.
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