![Linus Torvalds](/assets/img/avatar_default.png)
Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlzc+9QPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3o3sQAIJ2SZnITy/ycvkbhKe+V/806P+aoqMpbZDw 7ldBQFoIMQqVIoeSSeml+9B86ZGyK4CGTgnvsfAI/Zt2fZSHczjqLP5InbEnvB5M 4naf0nSjSlkb5F4p24wXQ7WTI8IO45SwqG4hCi/WW6MakxN21cwdMWHBn+TRZWQu +AlJdwyDFJoMRXcq8xvLHOBNVAqD3LyvlECbLKqn3+UPwwYw0Ti1dsLwaMLOYDbc o/1dC2O8111kg2DgO0OM4Tl7jdbpmGA5MeixbVnmu3t4b2s26trG33eXqK2yWqaV XigD85R74GAq/wmgnzjdiNaIgZjlPPitVYaTE4L6Od39zMgXemnsqMlh/byPeO2y JvRRLEIciNay9q9uq+8H2zRWwa2wLqAewjssTTMM0RJNQWUtonVCkD8DAx4GLDof 6Ej42XGbtxnqpf0g854mBJ4zaPfZLN4xK//1Llx9HkM8mhLZLJ7BQvgvW1JzniSa XKnmjqK7SySiJ4bbjn+aFk5EkX7Oh5aXno18tVNKXdxc8nWoEw4PHMUmCCHOFPye /1oxc95Ux8P/lV+B0ZjiI0yTAX/IpDkEszAYmgdy6pWh1hXnYUr/Rpm7cGUG8kzk SbtyB8JOI/DFQ7QMDfPp6e6bcB8zTbUuF9H2MXwPN5TqGzP/mya88DC5Iv1jY4jc 0oWv/uhj =YSfu -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits) soc: aspeed: fix Kconfig soc: add aspeed folder and misc drivers spi: zynqmp: Fix build break soc: imx: Add generic i.MX8 SoC driver MAINTAINERS: Update email for Qualcomm SoC maintainer memory: tegra: Fix a typos for "fdcdwr2" mc client Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" memory: tegra: Replace readl-writel with mc_readl-mc_writel memory: tegra: Fix integer overflow on tick value calculation memory: tegra: Fix missed registers values latching ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30 optee: allow to work without static shared memory soc/tegra: pmc: Move powergate initialisation to probe soc/tegra: pmc: Remove reset sysfs entries on error soc/tegra: pmc: Fix reset sources and levels soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask fpga manager: Adding FPGA Manager support for Xilinx zynqmp dt-bindings: fpga: Add bindings for ZynqMP fpga driver firmware: xilinx: Add fpga API's ...
445 lines
11 KiB
C
445 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Provides a simple driver to control the ASPEED P2A interface which allows
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* the host to read and write to various regions of the BMC's memory.
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*/
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#include <linux/fs.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/miscdevice.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/aspeed-p2a-ctrl.h>
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#define DEVICE_NAME "aspeed-p2a-ctrl"
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/* SCU2C is a Misc. Control Register. */
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#define SCU2C 0x2c
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/* SCU180 is the PCIe Configuration Setting Control Register. */
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#define SCU180 0x180
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/* Bit 1 controls the P2A bridge, while bit 0 controls the entire VGA device
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* on the PCI bus.
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*/
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#define SCU180_ENP2A BIT(1)
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/* The ast2400/2500 both have six ranges. */
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#define P2A_REGION_COUNT 6
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struct region {
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u64 min;
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u64 max;
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u32 bit;
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};
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struct aspeed_p2a_model_data {
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/* min, max, bit */
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struct region regions[P2A_REGION_COUNT];
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};
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struct aspeed_p2a_ctrl {
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struct miscdevice miscdev;
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struct regmap *regmap;
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const struct aspeed_p2a_model_data *config;
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/* Access to these needs to be locked, held via probe, mapping ioctl,
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* and release, remove.
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*/
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struct mutex tracking;
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u32 readers;
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u32 readerwriters[P2A_REGION_COUNT];
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phys_addr_t mem_base;
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resource_size_t mem_size;
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};
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struct aspeed_p2a_user {
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struct file *file;
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struct aspeed_p2a_ctrl *parent;
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/* The entire memory space is opened for reading once the bridge is
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* enabled, therefore this needs only to be tracked once per user.
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* If any user has it open for read, the bridge must stay enabled.
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*/
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u32 read;
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/* Each entry of the array corresponds to a P2A Region. If the user
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* opens for read or readwrite, the reference goes up here. On
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* release, this array is walked and references adjusted accordingly.
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*/
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u32 readwrite[P2A_REGION_COUNT];
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};
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static void aspeed_p2a_enable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
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{
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regmap_update_bits(p2a_ctrl->regmap,
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SCU180, SCU180_ENP2A, SCU180_ENP2A);
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}
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static void aspeed_p2a_disable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
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{
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regmap_update_bits(p2a_ctrl->regmap, SCU180, SCU180_ENP2A, 0);
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}
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static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
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{
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unsigned long vsize;
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pgprot_t prot;
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struct aspeed_p2a_user *priv = file->private_data;
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struct aspeed_p2a_ctrl *ctrl = priv->parent;
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if (ctrl->mem_base == 0 && ctrl->mem_size == 0)
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return -EINVAL;
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vsize = vma->vm_end - vma->vm_start;
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prot = vma->vm_page_prot;
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if (vma->vm_pgoff + vsize > ctrl->mem_base + ctrl->mem_size)
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return -EINVAL;
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/* ast2400/2500 AHB accesses are not cache coherent */
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prot = pgprot_noncached(prot);
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if (remap_pfn_range(vma, vma->vm_start,
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(ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
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vsize, prot))
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return -EAGAIN;
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return 0;
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}
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static bool aspeed_p2a_region_acquire(struct aspeed_p2a_user *priv,
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struct aspeed_p2a_ctrl *ctrl,
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struct aspeed_p2a_ctrl_mapping *map)
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{
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int i;
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u64 base, end;
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bool matched = false;
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base = map->addr;
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end = map->addr + (map->length - 1);
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/* If the value is a legal u32, it will find a match. */
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for (i = 0; i < P2A_REGION_COUNT; i++) {
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const struct region *curr = &ctrl->config->regions[i];
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/* If the top of this region is lower than your base, skip it.
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*/
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if (curr->max < base)
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continue;
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/* If the bottom of this region is higher than your end, bail.
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*/
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if (curr->min > end)
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break;
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/* Lock this and update it, therefore it someone else is
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* closing their file out, this'll preserve the increment.
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*/
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mutex_lock(&ctrl->tracking);
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ctrl->readerwriters[i] += 1;
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mutex_unlock(&ctrl->tracking);
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/* Track with the user, so when they close their file, we can
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* decrement properly.
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*/
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priv->readwrite[i] += 1;
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/* Enable the region as read-write. */
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regmap_update_bits(ctrl->regmap, SCU2C, curr->bit, 0);
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matched = true;
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}
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return matched;
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}
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static long aspeed_p2a_ioctl(struct file *file, unsigned int cmd,
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unsigned long data)
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{
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struct aspeed_p2a_user *priv = file->private_data;
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struct aspeed_p2a_ctrl *ctrl = priv->parent;
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void __user *arg = (void __user *)data;
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struct aspeed_p2a_ctrl_mapping map;
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if (copy_from_user(&map, arg, sizeof(map)))
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return -EFAULT;
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switch (cmd) {
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case ASPEED_P2A_CTRL_IOCTL_SET_WINDOW:
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/* If they want a region to be read-only, since the entire
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* region is read-only once enabled, we just need to track this
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* user wants to read from the bridge, and if it's not enabled.
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* Enable it.
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*/
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if (map.flags == ASPEED_P2A_CTRL_READ_ONLY) {
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mutex_lock(&ctrl->tracking);
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ctrl->readers += 1;
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mutex_unlock(&ctrl->tracking);
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/* Track with the user, so when they close their file,
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* we can decrement properly.
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*/
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priv->read += 1;
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} else if (map.flags == ASPEED_P2A_CTRL_READWRITE) {
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/* If we don't acquire any region return error. */
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if (!aspeed_p2a_region_acquire(priv, ctrl, &map)) {
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return -EINVAL;
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}
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} else {
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/* Invalid map flags. */
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return -EINVAL;
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}
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aspeed_p2a_enable_bridge(ctrl);
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return 0;
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case ASPEED_P2A_CTRL_IOCTL_GET_MEMORY_CONFIG:
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/* This is a request for the memory-region and corresponding
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* length that is used by the driver for mmap.
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*/
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map.flags = 0;
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map.addr = ctrl->mem_base;
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map.length = ctrl->mem_size;
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return copy_to_user(arg, &map, sizeof(map)) ? -EFAULT : 0;
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}
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return -EINVAL;
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}
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/*
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* When a user opens this file, we create a structure to track their mappings.
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*
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* A user can map a region as read-only (bridge enabled), or read-write (bit
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* flipped, and bridge enabled). Either way, this tracking is used, s.t. when
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* they release the device references are handled.
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*
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* The bridge is not enabled until a user calls an ioctl to map a region,
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* simply opening the device does not enable it.
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*/
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static int aspeed_p2a_open(struct inode *inode, struct file *file)
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{
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struct aspeed_p2a_user *priv;
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priv = kmalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->file = file;
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priv->read = 0;
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memset(priv->readwrite, 0, sizeof(priv->readwrite));
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/* The file's private_data is initialized to the p2a_ctrl. */
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priv->parent = file->private_data;
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/* Set the file's private_data to the user's data. */
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file->private_data = priv;
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return 0;
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}
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/*
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* This will close the users mappings. It will go through what they had opened
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* for readwrite, and decrement those counts. If at the end, this is the last
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* user, it'll close the bridge.
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*/
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static int aspeed_p2a_release(struct inode *inode, struct file *file)
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{
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int i;
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u32 bits = 0;
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bool open_regions = false;
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struct aspeed_p2a_user *priv = file->private_data;
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/* Lock others from changing these values until everything is updated
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* in one pass.
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*/
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mutex_lock(&priv->parent->tracking);
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priv->parent->readers -= priv->read;
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for (i = 0; i < P2A_REGION_COUNT; i++) {
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priv->parent->readerwriters[i] -= priv->readwrite[i];
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if (priv->parent->readerwriters[i] > 0)
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open_regions = true;
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else
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bits |= priv->parent->config->regions[i].bit;
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}
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/* Setting a bit to 1 disables the region, so let's just OR with the
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* above to disable any.
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*/
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/* Note, if another user is trying to ioctl, they can't grab tracking,
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* and therefore can't grab either register mutex.
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* If another user is trying to close, they can't grab tracking either.
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*/
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regmap_update_bits(priv->parent->regmap, SCU2C, bits, bits);
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/* If parent->readers is zero and open windows is 0, disable the
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* bridge.
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*/
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if (!open_regions && priv->parent->readers == 0)
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aspeed_p2a_disable_bridge(priv->parent);
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mutex_unlock(&priv->parent->tracking);
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kfree(priv);
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return 0;
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}
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static const struct file_operations aspeed_p2a_ctrl_fops = {
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.owner = THIS_MODULE,
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.mmap = aspeed_p2a_mmap,
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.unlocked_ioctl = aspeed_p2a_ioctl,
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.open = aspeed_p2a_open,
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.release = aspeed_p2a_release,
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};
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/* The regions are controlled by SCU2C */
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static void aspeed_p2a_disable_all(struct aspeed_p2a_ctrl *p2a_ctrl)
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{
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int i;
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u32 value = 0;
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for (i = 0; i < P2A_REGION_COUNT; i++)
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value |= p2a_ctrl->config->regions[i].bit;
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regmap_update_bits(p2a_ctrl->regmap, SCU2C, value, value);
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/* Disable the bridge. */
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aspeed_p2a_disable_bridge(p2a_ctrl);
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}
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static int aspeed_p2a_ctrl_probe(struct platform_device *pdev)
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{
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struct aspeed_p2a_ctrl *misc_ctrl;
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struct device *dev;
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struct resource resm;
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struct device_node *node;
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int rc = 0;
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dev = &pdev->dev;
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misc_ctrl = devm_kzalloc(dev, sizeof(*misc_ctrl), GFP_KERNEL);
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if (!misc_ctrl)
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return -ENOMEM;
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mutex_init(&misc_ctrl->tracking);
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/* optional. */
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node = of_parse_phandle(dev->of_node, "memory-region", 0);
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if (node) {
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rc = of_address_to_resource(node, 0, &resm);
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of_node_put(node);
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if (rc) {
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dev_err(dev, "Couldn't address to resource for reserved memory\n");
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return -ENODEV;
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}
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misc_ctrl->mem_size = resource_size(&resm);
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misc_ctrl->mem_base = resm.start;
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}
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misc_ctrl->regmap = syscon_node_to_regmap(pdev->dev.parent->of_node);
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if (IS_ERR(misc_ctrl->regmap)) {
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dev_err(dev, "Couldn't get regmap\n");
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return -ENODEV;
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}
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misc_ctrl->config = of_device_get_match_data(dev);
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dev_set_drvdata(&pdev->dev, misc_ctrl);
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aspeed_p2a_disable_all(misc_ctrl);
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misc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
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misc_ctrl->miscdev.name = DEVICE_NAME;
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misc_ctrl->miscdev.fops = &aspeed_p2a_ctrl_fops;
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misc_ctrl->miscdev.parent = dev;
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rc = misc_register(&misc_ctrl->miscdev);
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if (rc)
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dev_err(dev, "Unable to register device\n");
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return rc;
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}
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static int aspeed_p2a_ctrl_remove(struct platform_device *pdev)
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{
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struct aspeed_p2a_ctrl *p2a_ctrl = dev_get_drvdata(&pdev->dev);
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misc_deregister(&p2a_ctrl->miscdev);
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return 0;
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}
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#define SCU2C_DRAM BIT(25)
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#define SCU2C_SPI BIT(24)
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#define SCU2C_SOC BIT(23)
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#define SCU2C_FLASH BIT(22)
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static const struct aspeed_p2a_model_data ast2400_model_data = {
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.regions = {
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{0x00000000, 0x17FFFFFF, SCU2C_FLASH},
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{0x18000000, 0x1FFFFFFF, SCU2C_SOC},
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{0x20000000, 0x2FFFFFFF, SCU2C_FLASH},
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{0x30000000, 0x3FFFFFFF, SCU2C_SPI},
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{0x40000000, 0x5FFFFFFF, SCU2C_DRAM},
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{0x60000000, 0xFFFFFFFF, SCU2C_SOC},
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}
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};
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static const struct aspeed_p2a_model_data ast2500_model_data = {
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.regions = {
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{0x00000000, 0x0FFFFFFF, SCU2C_FLASH},
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{0x10000000, 0x1FFFFFFF, SCU2C_SOC},
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{0x20000000, 0x3FFFFFFF, SCU2C_FLASH},
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{0x40000000, 0x5FFFFFFF, SCU2C_SOC},
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{0x60000000, 0x7FFFFFFF, SCU2C_SPI},
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{0x80000000, 0xFFFFFFFF, SCU2C_DRAM},
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}
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};
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static const struct of_device_id aspeed_p2a_ctrl_match[] = {
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{ .compatible = "aspeed,ast2400-p2a-ctrl",
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.data = &ast2400_model_data },
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{ .compatible = "aspeed,ast2500-p2a-ctrl",
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.data = &ast2500_model_data },
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{ },
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};
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static struct platform_driver aspeed_p2a_ctrl_driver = {
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.driver = {
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.name = DEVICE_NAME,
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.of_match_table = aspeed_p2a_ctrl_match,
|
|
},
|
|
.probe = aspeed_p2a_ctrl_probe,
|
|
.remove = aspeed_p2a_ctrl_remove,
|
|
};
|
|
|
|
module_platform_driver(aspeed_p2a_ctrl_driver);
|
|
|
|
MODULE_DEVICE_TABLE(of, aspeed_p2a_ctrl_match);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Patrick Venture <venture@google.com>");
|
|
MODULE_DESCRIPTION("Control for aspeed 2400/2500 P2A VGA HOST to BMC mappings");
|