bdde3d3ec9
Add support for the power areas in the Renesas R-Car M3-W+ (R8A77961)
SoC to the R-Car System Controller driver.
R-Car M3-W+ (aka R-Car M3-W ES3.0) is very similar to R-Car
M3-W (R8A77960), which allows for both SoCs to share a driver:
- R-Car M3-W+ lacks the A2VC power area, so its area must be
nullified,
- The existing support for the SYSCEXTMASK register added in commit
9bd645af9d2a49ac ("soc: renesas: r8a7796-sysc: Fix power request
conflicts") applies to ES3.0 and later only.
As R-Car M3-W+ uses a different compatible value, differentiate
based on that, instead of on the ES version.
Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-7-geert+renesas@glider.be
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Renesas R-Car System Controller
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#ifndef __SOC_RENESAS_RCAR_SYSC_H__
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#define __SOC_RENESAS_RCAR_SYSC_H__
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#include <linux/types.h>
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/*
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* Power Domain flags
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*/
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#define PD_CPU BIT(0) /* Area contains main CPU core */
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#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
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#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
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#define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
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#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
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#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
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/*
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* Description of a Power Area
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*/
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struct rcar_sysc_area {
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const char *name;
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u16 chan_offs; /* Offset of PWRSR register for this area */
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u8 chan_bit; /* Bit in PWR* (except for PWRUP in PWRSR) */
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u8 isr_bit; /* Bit in SYSCI*R */
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int parent; /* -1 if none */
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unsigned int flags; /* See PD_* */
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};
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/*
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* SoC-specific Power Area Description
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*/
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struct rcar_sysc_info {
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int (*init)(void); /* Optional */
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const struct rcar_sysc_area *areas;
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unsigned int num_areas;
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/* Optional External Request Mask Register */
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u32 extmask_offs; /* SYSCEXTMASK register offset */
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u32 extmask_val; /* SYSCEXTMASK register mask value */
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};
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extern const struct rcar_sysc_info r8a7743_sysc_info;
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extern const struct rcar_sysc_info r8a7745_sysc_info;
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extern const struct rcar_sysc_info r8a77470_sysc_info;
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extern const struct rcar_sysc_info r8a774a1_sysc_info;
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extern const struct rcar_sysc_info r8a774b1_sysc_info;
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extern const struct rcar_sysc_info r8a774c0_sysc_info;
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extern const struct rcar_sysc_info r8a7779_sysc_info;
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extern const struct rcar_sysc_info r8a7790_sysc_info;
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extern const struct rcar_sysc_info r8a7791_sysc_info;
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extern const struct rcar_sysc_info r8a7792_sysc_info;
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extern const struct rcar_sysc_info r8a7794_sysc_info;
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extern struct rcar_sysc_info r8a7795_sysc_info;
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extern const struct rcar_sysc_info r8a77960_sysc_info;
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extern const struct rcar_sysc_info r8a77961_sysc_info;
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extern const struct rcar_sysc_info r8a77965_sysc_info;
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extern const struct rcar_sysc_info r8a77970_sysc_info;
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extern const struct rcar_sysc_info r8a77980_sysc_info;
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extern const struct rcar_sysc_info r8a77990_sysc_info;
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extern const struct rcar_sysc_info r8a77995_sysc_info;
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/*
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* Helpers for fixing up power area tables depending on SoC revision
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*/
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extern void rcar_sysc_nullify(struct rcar_sysc_area *areas,
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unsigned int num_areas, u8 id);
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#endif /* __SOC_RENESAS_RCAR_SYSC_H__ */
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