![Tony Lindgren](/assets/img/avatar_default.png)
We've had generic code handling module sysconfig and OCP reset registers for omap variants for many years now and all the drivers really needs to do is just call runtime PM functions. Looks like the omap-hdq driver got only partially updated over the years to use runtime PM, and still has lots of custom PM code left. We can replace all the custom code for sysconfig, OCP reset, and PM with just a few lines of runtime PM autosuspend code. In order to set the device mode properly when pm_runtime_get_sync() is called during probe, we need to also move parsing of "ti,mode" to happen earlier before we call pm_runtime_enable(). Since we now disable interrupts lazily in omap_hdq_runtime_suspend(), we must remove the call to hdq_disable_interrupt() in omap_w1_read_byte(). And we must clear irqstatus calling wait_event_timeout() on it, so let's add hdq_reset_irqstatus() for that. Note that the earlier driver specific usage count limit of four seems completely artificial and should not be an issue in normal use. Cc: Adam Ford <aford173@gmail.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Andreas Kemnade <andreas@kemnade.info> Cc: H. Nikolaus Schaller <hns@goldelico.com> Cc: Vignesh R <vigneshr@ti.com> Tested-by: Andreas Kemnade <andreas@kemnade.info> # gta04 Tested-by: Adam Ford <aford173@gmail.com> #logicpd-torpedo-37xx-devkit Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20191217004048.46298-1-tony@atomide.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
667 lines
16 KiB
C
667 lines
16 KiB
C
/*
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* drivers/w1/masters/omap_hdq.c
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*
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* Copyright (C) 2007,2012 Texas Instruments, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/w1.h>
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#define MOD_NAME "OMAP_HDQ:"
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#define OMAP_HDQ_REVISION 0x00
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#define OMAP_HDQ_TX_DATA 0x04
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#define OMAP_HDQ_RX_DATA 0x08
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#define OMAP_HDQ_CTRL_STATUS 0x0c
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#define OMAP_HDQ_CTRL_STATUS_SINGLE BIT(7)
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#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK BIT(6)
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#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE BIT(5)
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#define OMAP_HDQ_CTRL_STATUS_GO BIT(4)
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#define OMAP_HDQ_CTRL_STATUS_PRESENCE BIT(3)
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#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION BIT(2)
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#define OMAP_HDQ_CTRL_STATUS_DIR BIT(1)
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#define OMAP_HDQ_INT_STATUS 0x10
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#define OMAP_HDQ_INT_STATUS_TXCOMPLETE BIT(2)
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#define OMAP_HDQ_INT_STATUS_RXCOMPLETE BIT(1)
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#define OMAP_HDQ_INT_STATUS_TIMEOUT BIT(0)
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#define OMAP_HDQ_FLAG_CLEAR 0
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#define OMAP_HDQ_FLAG_SET 1
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#define OMAP_HDQ_TIMEOUT (HZ/5)
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#define OMAP_HDQ_MAX_USER 4
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static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
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static int w1_id;
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module_param(w1_id, int, S_IRUSR);
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MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode");
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struct hdq_data {
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struct device *dev;
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void __iomem *hdq_base;
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/* lock status update */
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struct mutex hdq_mutex;
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u8 hdq_irqstatus;
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/* device lock */
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spinlock_t hdq_spinlock;
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/* mode: 0-HDQ 1-W1 */
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int mode;
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};
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/* HDQ register I/O routines */
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static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
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{
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return __raw_readl(hdq_data->hdq_base + offset);
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}
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static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
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{
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__raw_writel(val, hdq_data->hdq_base + offset);
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}
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static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
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u8 val, u8 mask)
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{
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u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
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| (val & mask);
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__raw_writel(new_val, hdq_data->hdq_base + offset);
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return new_val;
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}
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/*
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* Wait for one or more bits in flag change.
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* HDQ_FLAG_SET: wait until any bit in the flag is set.
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* HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
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* return 0 on success and -ETIMEDOUT in the case of timeout.
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*/
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static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
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u8 flag, u8 flag_set, u8 *status)
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{
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int ret = 0;
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unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
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if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
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/* wait for the flag clear */
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while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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if (*status & flag)
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ret = -ETIMEDOUT;
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} else if (flag_set == OMAP_HDQ_FLAG_SET) {
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/* wait for the flag set */
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while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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if (!(*status & flag))
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ret = -ETIMEDOUT;
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} else
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return -EINVAL;
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return ret;
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}
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/* Clear saved irqstatus after using an interrupt */
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static void hdq_reset_irqstatus(struct hdq_data *hdq_data)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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hdq_data->hdq_irqstatus = 0;
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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}
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/* write out a byte and fill *status with HDQ_INT_STATUS */
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static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
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{
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int ret;
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u8 tmp_status;
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*status = 0;
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hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
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/* set the GO bit */
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
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/* wait for the TXCOMPLETE bit */
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ret = wait_event_timeout(hdq_wait_queue,
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hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
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if (ret == 0) {
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dev_dbg(hdq_data->dev, "TX wait elapsed\n");
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ret = -ETIMEDOUT;
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goto out;
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}
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*status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
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dev_dbg(hdq_data->dev, "timeout waiting for"
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" TXCOMPLETE/RXCOMPLETE, %x", *status);
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ret = -ETIMEDOUT;
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goto out;
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}
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/* wait for the GO bit return to zero */
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ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_FLAG_CLEAR, &tmp_status);
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if (ret) {
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dev_dbg(hdq_data->dev, "timeout waiting GO bit"
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" return to zero, %x", tmp_status);
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}
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out:
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hdq_reset_irqstatus(hdq_data);
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return ret;
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}
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/* HDQ Interrupt service routine */
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static irqreturn_t hdq_isr(int irq, void *_hdq)
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{
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struct hdq_data *hdq_data = _hdq;
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unsigned long irqflags;
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
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if (hdq_data->hdq_irqstatus &
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(OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
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| OMAP_HDQ_INT_STATUS_TIMEOUT)) {
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/* wake up sleeping process */
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wake_up(&hdq_wait_queue);
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}
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return IRQ_HANDLED;
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}
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/* W1 search callback function in HDQ mode */
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static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
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u8 search_type, w1_slave_found_callback slave_found)
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{
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u64 module_id, rn_le, cs, id;
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if (w1_id)
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module_id = w1_id;
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else
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module_id = 0x1;
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rn_le = cpu_to_le64(module_id);
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/*
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* HDQ might not obey truly the 1-wire spec.
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* So calculate CRC based on module parameter.
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*/
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cs = w1_calc_crc8((u8 *)&rn_le, 7);
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id = (cs << 56) | module_id;
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slave_found(master_dev, id);
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}
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/* Issue break pulse to the device */
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static int omap_hdq_break(struct hdq_data *hdq_data)
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{
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int ret = 0;
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u8 tmp_status;
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ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
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if (ret < 0) {
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dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
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ret = -EINTR;
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goto rtn;
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}
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/* set the INIT and GO bit */
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
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OMAP_HDQ_CTRL_STATUS_GO);
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/* wait for the TIMEOUT bit */
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ret = wait_event_timeout(hdq_wait_queue,
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hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
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if (ret == 0) {
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dev_dbg(hdq_data->dev, "break wait elapsed\n");
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ret = -EINTR;
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goto out;
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}
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tmp_status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
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dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
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tmp_status);
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ret = -ETIMEDOUT;
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goto out;
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}
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/*
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* check for the presence detect bit to get
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* set to show that the slave is responding
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*/
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if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) &
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OMAP_HDQ_CTRL_STATUS_PRESENCE)) {
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dev_dbg(hdq_data->dev, "Presence bit not set\n");
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ret = -ETIMEDOUT;
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goto out;
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}
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/*
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* wait for both INIT and GO bits rerurn to zero.
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* zero wait time expected for interrupt mode.
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*/
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ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
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OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
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&tmp_status);
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if (ret)
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dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
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" return to zero, %x", tmp_status);
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out:
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hdq_reset_irqstatus(hdq_data);
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mutex_unlock(&hdq_data->hdq_mutex);
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rtn:
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return ret;
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}
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static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
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{
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int ret = 0;
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u8 status;
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ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
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if (ret < 0) {
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ret = -EINTR;
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goto rtn;
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}
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if (pm_runtime_suspended(hdq_data->dev)) {
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ret = -EINVAL;
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goto out;
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}
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if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
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/*
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* The RX comes immediately after TX.
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*/
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wait_event_timeout(hdq_wait_queue,
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(hdq_data->hdq_irqstatus
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& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
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OMAP_HDQ_TIMEOUT);
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
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OMAP_HDQ_CTRL_STATUS_DIR);
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status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
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dev_dbg(hdq_data->dev, "timeout waiting for"
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" RXCOMPLETE, %x", status);
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ret = -ETIMEDOUT;
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goto out;
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}
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}
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/* the data is ready. Read it in! */
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*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
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out:
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hdq_reset_irqstatus(hdq_data);
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mutex_unlock(&hdq_data->hdq_mutex);
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rtn:
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return ret;
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}
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/*
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* W1 triplet callback function - used for searching ROM addresses.
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* Registered only when controller is in 1-wire mode.
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*/
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static u8 omap_w1_triplet(void *_hdq, u8 bdir)
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{
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u8 id_bit, comp_bit;
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int err;
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u8 ret = 0x3; /* no slaves responded */
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struct hdq_data *hdq_data = _hdq;
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u8 ctrl = OMAP_HDQ_CTRL_STATUS_SINGLE | OMAP_HDQ_CTRL_STATUS_GO |
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OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK;
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u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR;
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err = pm_runtime_get_sync(hdq_data->dev);
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if (err < 0) {
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pm_runtime_put_noidle(hdq_data->dev);
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return err;
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}
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err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
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if (err < 0) {
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dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
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goto rtn;
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}
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/* read id_bit */
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hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
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ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
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err = wait_event_timeout(hdq_wait_queue,
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(hdq_data->hdq_irqstatus
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& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
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OMAP_HDQ_TIMEOUT);
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if (err == 0) {
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dev_dbg(hdq_data->dev, "RX wait elapsed\n");
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goto out;
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}
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id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
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/* Must clear irqstatus for another RXCOMPLETE interrupt */
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hdq_reset_irqstatus(hdq_data);
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/* read comp_bit */
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hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
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ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
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err = wait_event_timeout(hdq_wait_queue,
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(hdq_data->hdq_irqstatus
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& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
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OMAP_HDQ_TIMEOUT);
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if (err == 0) {
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dev_dbg(hdq_data->dev, "RX wait elapsed\n");
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goto out;
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}
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comp_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
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if (id_bit && comp_bit) {
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ret = 0x03; /* no slaves responded */
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goto out;
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}
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if (!id_bit && !comp_bit) {
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/* Both bits are valid, take the direction given */
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ret = bdir ? 0x04 : 0;
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} else {
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/* Only one bit is valid, take that direction */
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bdir = id_bit;
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ret = id_bit ? 0x05 : 0x02;
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}
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/* write bdir bit */
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hdq_reg_out(_hdq, OMAP_HDQ_TX_DATA, bdir);
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hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl, mask);
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err = wait_event_timeout(hdq_wait_queue,
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(hdq_data->hdq_irqstatus
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& OMAP_HDQ_INT_STATUS_TXCOMPLETE),
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OMAP_HDQ_TIMEOUT);
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if (err == 0) {
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dev_dbg(hdq_data->dev, "TX wait elapsed\n");
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goto out;
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}
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hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 0,
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OMAP_HDQ_CTRL_STATUS_SINGLE);
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out:
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hdq_reset_irqstatus(hdq_data);
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mutex_unlock(&hdq_data->hdq_mutex);
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rtn:
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pm_runtime_mark_last_busy(hdq_data->dev);
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pm_runtime_put_autosuspend(hdq_data->dev);
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return ret;
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}
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/* reset callback */
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static u8 omap_w1_reset_bus(void *_hdq)
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{
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struct hdq_data *hdq_data = _hdq;
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int err;
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err = pm_runtime_get_sync(hdq_data->dev);
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if (err < 0) {
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pm_runtime_put_noidle(hdq_data->dev);
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return err;
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}
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omap_hdq_break(hdq_data);
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pm_runtime_mark_last_busy(hdq_data->dev);
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pm_runtime_put_autosuspend(hdq_data->dev);
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return 0;
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}
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|
|
/* Read a byte of data from the device */
|
|
static u8 omap_w1_read_byte(void *_hdq)
|
|
{
|
|
struct hdq_data *hdq_data = _hdq;
|
|
u8 val = 0;
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(hdq_data->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(hdq_data->dev);
|
|
|
|
return -1;
|
|
}
|
|
|
|
ret = hdq_read_byte(hdq_data, &val);
|
|
if (ret)
|
|
ret = -1;
|
|
|
|
pm_runtime_mark_last_busy(hdq_data->dev);
|
|
pm_runtime_put_autosuspend(hdq_data->dev);
|
|
|
|
return val;
|
|
}
|
|
|
|
/* Write a byte of data to the device */
|
|
static void omap_w1_write_byte(void *_hdq, u8 byte)
|
|
{
|
|
struct hdq_data *hdq_data = _hdq;
|
|
int ret;
|
|
u8 status;
|
|
|
|
ret = pm_runtime_get_sync(hdq_data->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(hdq_data->dev);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* We need to reset the slave before
|
|
* issuing the SKIP ROM command, else
|
|
* the slave will not work.
|
|
*/
|
|
if (byte == W1_SKIP_ROM)
|
|
omap_hdq_break(hdq_data);
|
|
|
|
ret = hdq_write_byte(hdq_data, byte, &status);
|
|
if (ret < 0) {
|
|
dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
|
|
goto out_err;
|
|
}
|
|
|
|
out_err:
|
|
pm_runtime_mark_last_busy(hdq_data->dev);
|
|
pm_runtime_put_autosuspend(hdq_data->dev);
|
|
}
|
|
|
|
static struct w1_bus_master omap_w1_master = {
|
|
.read_byte = omap_w1_read_byte,
|
|
.write_byte = omap_w1_write_byte,
|
|
.reset_bus = omap_w1_reset_bus,
|
|
};
|
|
|
|
static int __maybe_unused omap_hdq_runtime_suspend(struct device *dev)
|
|
{
|
|
struct hdq_data *hdq_data = dev_get_drvdata(dev);
|
|
|
|
hdq_reg_out(hdq_data, 0, hdq_data->mode);
|
|
hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused omap_hdq_runtime_resume(struct device *dev)
|
|
{
|
|
struct hdq_data *hdq_data = dev_get_drvdata(dev);
|
|
|
|
/* select HDQ/1W mode & enable clocks */
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
|
|
OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
|
|
hdq_data->mode);
|
|
hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops omap_hdq_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(omap_hdq_runtime_suspend,
|
|
omap_hdq_runtime_resume, NULL)
|
|
};
|
|
|
|
static int omap_hdq_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct hdq_data *hdq_data;
|
|
int ret, irq;
|
|
u8 rev;
|
|
const char *mode;
|
|
|
|
hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
|
|
if (!hdq_data) {
|
|
dev_dbg(&pdev->dev, "unable to allocate memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
hdq_data->dev = dev;
|
|
platform_set_drvdata(pdev, hdq_data);
|
|
|
|
hdq_data->hdq_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(hdq_data->hdq_base))
|
|
return PTR_ERR(hdq_data->hdq_base);
|
|
|
|
mutex_init(&hdq_data->hdq_mutex);
|
|
|
|
ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode);
|
|
if (ret < 0 || !strcmp(mode, "hdq")) {
|
|
hdq_data->mode = 0;
|
|
omap_w1_master.search = omap_w1_search_bus;
|
|
} else {
|
|
hdq_data->mode = 1;
|
|
omap_w1_master.triplet = omap_w1_triplet;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 300);
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n");
|
|
goto err_w1;
|
|
}
|
|
|
|
rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
|
|
dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
|
|
(rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
|
|
|
|
spin_lock_init(&hdq_data->hdq_spinlock);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_dbg(&pdev->dev, "Failed to get IRQ: %d\n", irq);
|
|
ret = irq;
|
|
goto err_irq;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "could not request irq\n");
|
|
goto err_irq;
|
|
}
|
|
|
|
omap_hdq_break(hdq_data);
|
|
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
omap_w1_master.data = hdq_data;
|
|
|
|
ret = w1_add_master_device(&omap_w1_master);
|
|
if (ret) {
|
|
dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
|
|
goto err_w1;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_irq:
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
err_w1:
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int omap_hdq_remove(struct platform_device *pdev)
|
|
{
|
|
int active;
|
|
|
|
active = pm_runtime_get_sync(&pdev->dev);
|
|
if (active < 0)
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
w1_remove_master_device(&omap_w1_master);
|
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
if (active >= 0)
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id omap_hdq_dt_ids[] = {
|
|
{ .compatible = "ti,omap3-1w" },
|
|
{ .compatible = "ti,am4372-hdq" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, omap_hdq_dt_ids);
|
|
|
|
static struct platform_driver omap_hdq_driver = {
|
|
.probe = omap_hdq_probe,
|
|
.remove = omap_hdq_remove,
|
|
.driver = {
|
|
.name = "omap_hdq",
|
|
.of_match_table = omap_hdq_dt_ids,
|
|
.pm = &omap_hdq_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(omap_hdq_driver);
|
|
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
MODULE_DESCRIPTION("HDQ-1W driver Library");
|
|
MODULE_LICENSE("GPL");
|