cca851d7b4
The msysclk clock was checking for the wrong PLL for the parent in s3c2412_setparent_msysclk(), trying the UPLL instead of the MPLL output. Also ensure the mpll and fclks are at the same rate at init time. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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