![Dave Martin](/assets/img/avatar_default.png)
This patch implements the power_down_finish() method for TC2, to
enable the kernel to confirm when CPUs are safely powered down.
The information required for determining when a CPU is parked
cannot be obtained from any single place, so a few sources of
information must be combined:
* mcpm_cpu_power_down() must be pending for the CPU, so that we
don't get confused by false STANDBYWFI positives arising from
CPUidle. This is detected by waiting for the tc2_pm use count
for the target CPU to reach 0.
* Either the SPC must report that the CPU has asserted
STANDBYWFI, or the TC2 tile's reset control logic must be
holding the CPU in reset.
Just checking for STANDBYWFI is not sufficient, because this
signal is not latched when the the cluster is clamped off and
powered down: the relevant status bits just drop to zero. This
means that STANDBYWFI status cannot be used for reliable
detection of the last CPU in a cluster reaching WFI.
This patch is required in order for kexec to work with MCPM on TC2.
MCPM code was changed in commit 0de0d64675
('ARM: 7848/1: mcpm:
Implement cpu_kill() to synchronise on powerdown'), and since then it
will hit a WARN_ON_ONCE() due to power_down_finish not being implemented
on the TC2 platform.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
379 lines
9.7 KiB
C
379 lines
9.7 KiB
C
/*
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* arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
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*
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* Created by: Nicolas Pitre, October 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*
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* Some portions of this file were originally written by Achin Gupta
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* Copyright: (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <linux/arm-cci.h>
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#include "spc.h"
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/* SCC conf registers */
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#define RESET_CTRL 0x018
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#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu)))
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#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu)))
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#define A15_CONF 0x400
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#define A7_CONF 0x500
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#define SYS_INFO 0x700
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#define SPC_BASE 0xb00
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static void __iomem *scc;
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/*
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* We can't use regular spinlocks. In the switcher case, it is possible
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* for an outbound CPU to call power_down() after its inbound counterpart
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* is already live using the same logical CPU number which trips lockdep
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* debugging.
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*/
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static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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#define TC2_CLUSTERS 2
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#define TC2_MAX_CPUS_PER_CLUSTER 3
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static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
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/* Keep per-cpu usage count to cope with unordered up/down requests */
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static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
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#define tc2_cluster_unused(cluster) \
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(!tc2_pm_use_count[0][cluster] && \
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!tc2_pm_use_count[1][cluster] && \
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!tc2_pm_use_count[2][cluster])
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static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
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return -EINVAL;
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/*
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* Since this is called with IRQs enabled, and no arch_spin_lock_irq
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* variant exists, we need to disable IRQs manually here.
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*/
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local_irq_disable();
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arch_spin_lock(&tc2_pm_lock);
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if (tc2_cluster_unused(cluster))
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ve_spc_powerdown(cluster, false);
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tc2_pm_use_count[cpu][cluster]++;
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if (tc2_pm_use_count[cpu][cluster] == 1) {
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ve_spc_set_resume_addr(cluster, cpu,
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virt_to_phys(mcpm_entry_point));
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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} else if (tc2_pm_use_count[cpu][cluster] != 2) {
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/*
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* The only possible values are:
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* 0 = CPU down
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* 1 = CPU (still) up
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* 2 = CPU requested to be up before it had a chance
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* to actually make itself down.
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* Any other value is a bug.
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*/
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BUG();
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}
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arch_spin_unlock(&tc2_pm_lock);
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local_irq_enable();
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return 0;
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}
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static void tc2_pm_down(u64 residency)
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{
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unsigned int mpidr, cpu, cluster;
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bool last_man = false, skip_wfi = false;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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__mcpm_cpu_going_down(cpu, cluster);
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arch_spin_lock(&tc2_pm_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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tc2_pm_use_count[cpu][cluster]--;
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if (tc2_pm_use_count[cpu][cluster] == 0) {
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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if (tc2_cluster_unused(cluster)) {
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ve_spc_powerdown(cluster, true);
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ve_spc_global_wakeup_irq(true);
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last_man = true;
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}
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} else if (tc2_pm_use_count[cpu][cluster] == 1) {
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/*
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* A power_up request went ahead of us.
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* Even if we do not want to shut this CPU down,
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* the caller expects a certain state as if the WFI
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* was aborted. So let's continue with cache cleaning.
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*/
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skip_wfi = true;
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} else
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BUG();
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/*
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* If the CPU is committed to power down, make sure
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* the power controller will be in charge of waking it
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* up upon IRQ, ie IRQ lines are cut from GIC CPU IF
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* to the CPU by disabling the GIC CPU IF to prevent wfi
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* from completing execution behind power controller back
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*/
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if (!skip_wfi)
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gic_cpu_if_down();
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&tc2_pm_lock);
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3 \n\t"
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"isb \n\t"
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"dsb "
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: : "r" (0x400) );
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}
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v7_exit_coherency_flush(all);
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cci_disable_port_by_cpu(mpidr);
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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/*
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* If last man then undo any setup done previously.
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*/
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if (last_man) {
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ve_spc_powerdown(cluster, false);
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ve_spc_global_wakeup_irq(false);
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}
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arch_spin_unlock(&tc2_pm_lock);
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v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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/* Now we are prepared for power-down, do it: */
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if (!skip_wfi)
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wfi();
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/* Not dead at this point? Let our caller cope. */
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}
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static void tc2_pm_power_down(void)
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{
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tc2_pm_down(0);
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}
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static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
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{
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u32 mask = cluster ?
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RESET_A7_NCORERESET(cpu)
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: RESET_A15_NCORERESET(cpu);
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return !(readl_relaxed(scc + RESET_CTRL) & mask);
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}
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#define POLL_MSEC 10
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#define TIMEOUT_MSEC 1000
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static int tc2_pm_power_down_finish(unsigned int cpu, unsigned int cluster)
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{
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unsigned tries;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
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/*
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* Only examine the hardware state if the target CPU has
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* caught up at least as far as tc2_pm_down():
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*/
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if (ACCESS_ONCE(tc2_pm_use_count[cpu][cluster]) == 0) {
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pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
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__func__, cpu, cluster,
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readl_relaxed(scc + RESET_CTRL));
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/*
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* We need the CPU to reach WFI, but the power
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* controller may put the cluster in reset and
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* power it off as soon as that happens, before
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* we have a chance to see STANDBYWFI.
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*
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* So we need to check for both conditions:
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*/
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if (tc2_core_in_reset(cpu, cluster) ||
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ve_spc_cpu_in_wfi(cpu, cluster))
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return 0; /* success: the CPU is halted */
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}
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/* Otherwise, wait and retry: */
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msleep(POLL_MSEC);
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}
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return -ETIMEDOUT; /* timeout */
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}
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static void tc2_pm_suspend(u64 residency)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
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tc2_pm_down(residency);
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}
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static void tc2_pm_powered_up(void)
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{
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unsigned int mpidr, cpu, cluster;
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unsigned long flags;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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local_irq_save(flags);
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arch_spin_lock(&tc2_pm_lock);
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if (tc2_cluster_unused(cluster)) {
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ve_spc_powerdown(cluster, false);
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ve_spc_global_wakeup_irq(false);
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}
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if (!tc2_pm_use_count[cpu][cluster])
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tc2_pm_use_count[cpu][cluster] = 1;
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ve_spc_cpu_wakeup_irq(cluster, cpu, false);
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ve_spc_set_resume_addr(cluster, cpu, 0);
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arch_spin_unlock(&tc2_pm_lock);
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local_irq_restore(flags);
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}
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static const struct mcpm_platform_ops tc2_pm_power_ops = {
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.power_up = tc2_pm_power_up,
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.power_down = tc2_pm_power_down,
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.power_down_finish = tc2_pm_power_down_finish,
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.suspend = tc2_pm_suspend,
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.powered_up = tc2_pm_powered_up,
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};
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static bool __init tc2_pm_usage_count_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
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pr_err("%s: boot CPU is out of bound!\n", __func__);
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return false;
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}
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tc2_pm_use_count[cpu][cluster] = 1;
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return true;
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}
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*/
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static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
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{
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asm volatile (" \n"
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" cmp r0, #1 \n"
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" bxne lr \n"
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" b cci_enable_port_for_self ");
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}
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static int __init tc2_pm_init(void)
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{
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int ret, irq;
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u32 a15_cluster_id, a7_cluster_id, sys_info;
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struct device_node *np;
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/*
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* The power management-related features are hidden behind
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* SCC registers. We need to extract runtime information like
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* cluster ids and number of CPUs really available in clusters.
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*/
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np = of_find_compatible_node(NULL, NULL,
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"arm,vexpress-scc,v2p-ca15_a7");
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scc = of_iomap(np, 0);
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if (!scc)
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return -ENODEV;
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a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
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a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
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if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
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return -EINVAL;
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sys_info = readl_relaxed(scc + SYS_INFO);
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tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
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tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
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irq = irq_of_parse_and_map(np, 0);
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/*
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* A subset of the SCC registers is also used to communicate
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* with the SPC (power controller). We need to be able to
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* drive it very early in the boot process to power up
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* processors, so we initialize the SPC driver here.
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*/
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ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq);
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if (ret)
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return ret;
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if (!cci_probed())
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return -ENODEV;
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if (!tc2_pm_usage_count_init())
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return -EINVAL;
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ret = mcpm_platform_register(&tc2_pm_power_ops);
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if (!ret) {
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mcpm_sync_init(tc2_pm_power_up_setup);
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pr_info("TC2 power management initialized\n");
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}
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return ret;
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}
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early_initcall(tc2_pm_init);
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