![Alexander Beregalov](/assets/img/avatar_default.png)
Signed-off-by: Alexander Beregalov <a.beregalov@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
430 lines
22 KiB
C
430 lines
22 KiB
C
#ifndef _INC_MUSYCC_H_
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#define _INC_MUSYCC_H_
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/*-----------------------------------------------------------------------------
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* musycc.h - Multichannel Synchronous Communications Controller
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* CN8778/8474A/8472A/8471A
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*
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* Copyright (C) 2002-2005 SBE, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* For further information, contact via email: support@sbei.com
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* SBE, Inc. San Ramon, California U.S.A.
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*-----------------------------------------------------------------------------
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*/
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#include <linux/types.h>
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#define VINT8 volatile u_int8_t
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#define VINT32 volatile u_int32_t
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#include "pmcc4_defs.h"
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/*------------------------------------------------------------------------
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// Vendor, Board Identification definitions
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//------------------------------------------------------------------------
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*/
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#define PCI_VENDOR_ID_CONEXANT 0x14f1
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#define PCI_DEVICE_ID_CN8471 0x8471
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#define PCI_DEVICE_ID_CN8472 0x8472
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#define PCI_DEVICE_ID_CN8474 0x8474
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#define PCI_DEVICE_ID_CN8478 0x8478
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#define PCI_DEVICE_ID_CN8500 0x8500
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#define PCI_DEVICE_ID_CN8501 0x8501
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#define PCI_DEVICE_ID_CN8502 0x8502
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#define PCI_DEVICE_ID_CN8503 0x8503
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#define INT_QUEUE_SIZE MUSYCC_NIQD
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/* RAM image of MUSYCC registers laid out as a C structure */
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struct musycc_groupr
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{
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VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
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VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
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VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
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VINT32 rmp[32]; /* Receive Message Pointer [5-30] */
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VINT8 ttsm[128]; /* Time Slot Map [5-22] */
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VINT8 tscm[256]; /* Subchannel Map [5-24] */
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VINT32 tcct[32]; /* Channel Configuration [5-26] */
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VINT8 rtsm[128]; /* Time Slot Map [5-22] */
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VINT8 rscm[256]; /* Subchannel Map [5-24] */
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VINT32 rcct[32]; /* Channel Configuration [5-26] */
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VINT32 __glcd; /* Global Configuration Descriptor [5-10] */
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VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */
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VINT32 __iql; /* Interrupt Queue Length [5-36] */
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VINT32 grcd; /* Group Configuration Descriptor [5-16] */
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VINT32 mpd; /* Memory Protection Descriptor [5-18] */
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VINT32 mld; /* Message Length Descriptor [5-20] */
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VINT32 pcd; /* Port Configuration Descriptor [5-19] */
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};
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/* hardware MUSYCC registers laid out as a C structure */
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struct musycc_globalr
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{
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VINT32 gbp; /* Group Base Pointer */
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VINT32 dacbp; /* Dual Address Cycle Base Pointer */
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VINT32 srd; /* Service Request Descriptor */
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VINT32 isd; /* Interrupt Service Descriptor */
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/*
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* adjust __thp due to above 4 registers, which are not contained
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* within musycc_groupr[]. All __XXX[] are just place holders,
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* anyhow.
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*/
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VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */
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VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */
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VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */
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VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */
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VINT8 ttsm[128]; /* Time Slot Map [5-22] */
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VINT8 tscm[256]; /* Subchannel Map [5-24] */
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VINT32 tcct[32]; /* Channel Configuration [5-26] */
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VINT8 rtsm[128]; /* Time Slot Map [5-22] */
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VINT8 rscm[256]; /* Subchannel Map [5-24] */
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VINT32 rcct[32]; /* Channel Configuration [5-26] */
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VINT32 glcd; /* Global Configuration Descriptor [5-10] */
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VINT32 iqp; /* Interrupt Queue Pointer [5-36] */
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VINT32 iql; /* Interrupt Queue Length [5-36] */
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VINT32 grcd; /* Group Configuration Descriptor [5-16] */
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VINT32 mpd; /* Memory Protection Descriptor [5-18] */
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VINT32 mld; /* Message Length Descriptor [5-20] */
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VINT32 pcd; /* Port Configuration Descriptor [5-19] */
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VINT32 rbist; /* Receive BIST status [5-4] */
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VINT32 tbist; /* Receive BIST status [5-4] */
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};
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/* Global Config Descriptor bit macros */
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#define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */
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#define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */
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#define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */
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#define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */
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#define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit
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* field */
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#define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit
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* field */
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#define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit
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* field */
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#define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */
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#define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp
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* 4,5,6,7 */
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#define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3,
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* etc... */
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#define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2,
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* etc... */
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/* and board specific assignments... */
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#ifdef SBE_WAN256T3_ENABLE
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#define BLAPSE_VAL 0
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#define ALAPSE_VAL 0
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#define ELAPSE_VAL 7
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#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_2
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#endif
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#ifdef SBE_PMCC4_ENABLE
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#define BLAPSE_VAL 7
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#define ALAPSE_VAL 3
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#define ELAPSE_VAL 7
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#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_0
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#endif
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#define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \
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((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \
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((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \
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(MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL)
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/* Group Config Descriptor bit macros */
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#define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */
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#define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */
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#define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for
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* subchanneling */
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#define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message
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* processing disabled all
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* channels */
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#define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs
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* disabled */
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#define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment
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* irq disabled */
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#define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status
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* overwrite disabled */
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#define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status
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* overwrite disabled */
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#define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */
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#define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits
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* copy enable. Conexant sez
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* turn this on */
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#define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */
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#define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */
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#define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */
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#define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle
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* bit field */
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#define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM
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* count threshold */
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/* Port Config Descriptor bit macros */
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#define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */
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#define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */
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#define MUSYCC_PCD_NX64_MODE 4
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#define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK
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* rising edge */
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#define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on
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* TCLK rising edge */
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#define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK
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* rising edge */
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#define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on
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* RCLK rising edge */
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#define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame
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* signal on RCLK rising edge */
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#define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes
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* logic 1 on output, else
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* tristate */
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#define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode
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* between E1 and T1 */
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/* Time Slot Descriptor bit macros */
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#define MUSYCC_TSD_MODE_64KBPS 4
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#define MUSYCC_TSD_MODE_56KBPS 5
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#define MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6
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#define MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7
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/* Message Descriptor bit macros */
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#define MUSYCC_MDT_BASE03_ADDR 0x00006000
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/* Channel Config Descriptor bit macros */
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#define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */
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#define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */
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#define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT
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* irqs disabled */
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#define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs
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* disabled */
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#define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */
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#define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */
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#define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */
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#define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */
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#define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with
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* received data */
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#define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit
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* field */
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#define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */
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#define MUSYCC_CCD_SS7 1
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#define MUSYCC_CCD_HDLC_FCS16 2
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#define MUSYCC_CCD_HDLC_FCS32 3
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#define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */
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#define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */
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#define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit
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* field */
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#define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data
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* buffer length */
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#define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data
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* buffer starting location */
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/****************************************************************************
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* Interrupt Descriptor Information */
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#define INT_EMPTY_ENTRY 0xfeedface
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#define INT_EMPTY_ENTRY2 0xdeadface
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/****************************************************************************
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* Interrupt Status Descriptor
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*
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* NOTE: One must first fetch the value of the interrupt status descriptor
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* into a local variable, then pass that value into the read macros. This
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* is required to avoid race conditions.
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***/
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#define INTRPTS_NEXTINT_M 0x7FFF0000
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#define INTRPTS_NEXTINT_S 16
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#define INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S)
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#define INTRPTS_INTFULL_M 0x00008000
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#define INTRPTS_INTFULL_S 15
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#define INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S)
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#define INTRPTS_INTCNT_M 0x00007FFF
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#define INTRPTS_INTCNT_S 0
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#define INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S)
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/****************************************************************************
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* Interrupt Descriptor
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***/
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#define INTRPT_DIR_M 0x80000000
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#define INTRPT_DIR_S 31
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#define INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S)
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#define INTRPT_GRP_M 0x60000000
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#define INTRPT_GRP_MSB_M 0x00004000
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#define INTRPT_GRP_S 29
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#define INTRPT_GRP_MSB_S 12
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#define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \
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((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S))
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#define INTRPT_CH_M 0x1F000000
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#define INTRPT_CH_S 24
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#define INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S)
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#define INTRPT_EVENT_M 0x00F00000
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#define INTRPT_EVENT_S 20
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#define INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S)
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#define INTRPT_ERROR_M 0x000F0000
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#define INTRPT_ERROR_S 16
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#define INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S)
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#define INTRPT_ILOST_M 0x00008000
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#define INTRPT_ILOST_S 15
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#define INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S)
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#define INTRPT_PERR_M 0x00004000
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#define INTRPT_PERR_S 14
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#define INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S)
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#define INTRPT_BLEN_M 0x00003FFF
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#define INTRPT_BLEN_S 0
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#define INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S)
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/* Buffer Descriptor bit macros */
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#define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host
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* owner on receive */
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#define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */
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#define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */
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#define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */
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#define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */
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#define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer
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* for ownership */
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#define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of
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* the message */
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#define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */
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#define PADFILL_ENABLE 0x01000000 /* Enable padfill */
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#define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */
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#define LENGTH_MASK 0X3fff /* This part of status descriptor is
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* length */
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#define IDLE_CODE 25 /* Position index for idle code (2
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* bits) */
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#define EXTRA_FLAGS 16 /* Position index for minimum flags
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* between messages (8 bits) */
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#define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the
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* pattern is OR'd in */
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#define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the
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* pattern is OR'd in */
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#define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on
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* the polled mode descriptor */
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/* Service Request Descriptor bit macros */
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#define SREQ 8 /* Position index for service request bit
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* field */
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#define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */
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#define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */
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#define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */
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#define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global
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* config deswc and interrupt
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* queue desc */
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#define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot
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* and Subchannel maps,
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* Channel Config, */
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/*
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* Group Config, Memory Protect, Message Length, and Port Config
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* Descriptors
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*/
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#define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head
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* Pointer, process first
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* Message Descriptor */
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#define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */
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#define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */
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#define SR_JUMP (10<<(SREQ)) /* a: Process new Message
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* List */
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#define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel
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* Configuration Descriptor */
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#define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global
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* Configuration Descriptor */
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#define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue
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* Descriptor */
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#define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group
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* Configuration Descriptor */
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#define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection
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* Descriptor */
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#define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length
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* Descriptor */
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#define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port
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* Configuration Descriptor */
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#define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */
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#define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */
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#define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel
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* Configuration Table for
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* the group */
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#define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit.
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* Bit off indicates receive
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* direction */
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#define SR_RX_DIRECTION 0x00000000
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/* Interrupt Descriptor bit macros */
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#define GROUP10 29 /* Position index for the 2 LS group
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* bits */
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#define CHANNEL 24 /* Position index for channel bits */
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#define INT_IQD_TX 0x80000000
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#define INT_IQD_GRP 0x60000000
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#define INT_IQD_CHAN 0x1f000000
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#define INT_IQD_EVENT 0x00f00000
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#define INT_IQD_ERROR 0x000f0000
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#define INT_IQD_ILOST 0x00008000
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#define INT_IQD_PERR 0x00004000
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#define INT_IQD_BLEN 0x00003fff
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/* Interrupt Descriptor Events */
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#define EVE_EVENT 20 /* Position index for event bits */
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#define EVE_NONE 0 /* No event to report in this
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* interrupt */
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#define EVE_SACK 1 /* Service Request acknowledge */
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#define EVE_EOB 2 /* End of Buffer */
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#define EVE_EOM 3 /* End of Message */
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#define EVE_EOP 4 /* End of Padfill */
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#define EVE_CHABT 5 /* Change to Abort Code */
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#define EVE_CHIC 6 /* Change to Idle Code */
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#define EVE_FREC 7 /* Frame Recovery */
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#define EVE_SINC 8 /* MTP2 SUERM Increment */
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#define EVE_SDEC 9 /* MTP2 SUERM Decrement */
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#define EVE_SFILT 10 /* MTP2 SUERM Filtered Message */
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/* Interrupt Descriptor Errors */
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#define ERR_ERRORS 16 /* Position index for error bits */
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#define ERR_BUF 1 /* Buffer Error */
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#define ERR_COFA 2 /* Change of Frame Alignment Error */
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#define ERR_ONR 3 /* Owner Bit Error */
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#define ERR_PROT 4 /* Memory Protection Error */
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#define ERR_OOF 8 /* Out of Frame Error */
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#define ERR_FCS 9 /* FCS Error */
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#define ERR_ALIGN 10 /* Octet Alignment Error */
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#define ERR_ABT 11 /* Abort Termination */
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#define ERR_LNG 12 /* Long Message Error */
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#define ERR_SHT 13 /* Short Message Error */
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#define ERR_SUERR 14 /* SUERM threshold exceeded */
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#define ERR_PERR 15 /* PCI Parity Error */
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/* Other Stuff */
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#define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off
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* indicates receive direction */
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#define ILOST 0x00008000 /* Interrupt Lost */
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#define GROUPMSB 0x00004000 /* Group number MSB */
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#define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */
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#define INITIAL_STATUS 0x10000 /* IRQ status should be this after
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* reset */
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/* This must be defined on an entire channel group (Port) basis */
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#define SUERM_THRESHOLD 0x1f
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#undef VINT32
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#undef VINT8
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#endif /*** _INC_MUSYCC_H_ ***/
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/*** End-of-File ***/
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