![Márton Németh](/assets/img/avatar_default.png)
This will remove the following checkpatch.pl error: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Márton Németh <nm127@freemail.hu> Acked-by: edwin_rong <edwin_rong@realsil.com.cn> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
905 lines
26 KiB
C
905 lines
26 KiB
C
/* Driver for Realtek RTS51xx USB card reader
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* Header file
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*
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* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* wwang (wei_wang@realsil.com.cn)
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* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
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* Maintainer:
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* Edwin Rong (edwin_rong@realsil.com.cn)
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* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
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*/
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#ifndef __RTS51X_CHIP_H
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#define __RTS51X_CHIP_H
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#include <linux/usb.h>
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#include <linux/usb_usual.h>
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#include <linux/blkdev.h>
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include <scsi/scsi_host.h>
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#include "trace.h"
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#define SUPPORT_CPRM
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#define SUPPORT_MAGIC_GATE
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#define SUPPORT_MSXC
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/* #define LED_AUTO_BLINK */
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/* { wwang, 2010-07-26
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* Add support for SD lock/unlock */
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/* #define SUPPORT_SD_LOCK */
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/* } wwang, 2010-07-26 */
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#ifdef SUPPORT_MAGIC_GA
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/* Using NORMAL_WRITE instead of AUTO_WRITE to set ICVTE */
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#define MG_SET_ICV_SLOW
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#endif
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#ifdef SUPPORT_MSXC
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#define XC_POWERCLASS
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#define SUPPORT_PCGL_1P18
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#endif
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#define GET_CARD_STATUS_USING_EPC
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#define CLOSE_SSC_POWER
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#define SUPPORT_OCP
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#define MS_SPEEDUP
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/* #define XD_SPEEDUP */
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#define SD_XD_IO_FOLLOW_PWR
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#define SD_NR 2
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#define MS_NR 3
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#define XD_NR 4
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#define SD_CARD (1 << SD_NR)
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#define MS_CARD (1 << MS_NR)
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#define XD_CARD (1 << XD_NR)
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#define SD_CD 0x01
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#define MS_CD 0x02
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#define XD_CD 0x04
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#define SD_WP 0x08
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#define MAX_ALLOWED_LUN_CNT 8
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#define CMD_BUF_LEN 1024
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#define RSP_BUF_LEN 1024
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#define POLLING_INTERVAL 50 /* 50ms */
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#define XD_FREE_TABLE_CNT 1200
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#define MS_FREE_TABLE_CNT 512
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/* Bit Operation */
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#define SET_BIT(data, idx) ((data) |= 1 << (idx))
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#define CLR_BIT(data, idx) ((data) &= ~(1 << (idx)))
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#define CHK_BIT(data, idx) ((data) & (1 << (idx)))
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/* Command type */
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#define READ_REG_CMD 0
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#define WRITE_REG_CMD 1
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#define CHECK_REG_CMD 2
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#define PACKET_TYPE 4
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#define CNT_H 5
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#define CNT_L 6
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#define STAGE_FLAG 7
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#define CMD_OFFSET 8
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/* Packet type */
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#define BATCH_CMD 0
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#define SEQ_READ 1
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#define SEQ_WRITE 2
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/* Stage flag */
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#define STAGE_R 0x01
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#define STAGE_DI 0x02
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#define STAGE_DO 0x04
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/* Return MS_TRANS_CFG, GET_INT */
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#define STAGE_MS_STATUS 0x08
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/* Return XD_CFG, XD_CTL, XD_PAGE_STATUS */
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#define STAGE_XD_STATUS 0x10
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/* Command stage mode */
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#define MODE_C 0x00
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#define MODE_CR (STAGE_R)
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#define MODE_CDIR (STAGE_R | STAGE_DI)
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#define MODE_CDOR (STAGE_R | STAGE_DO)
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/* Function return code */
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#ifndef STATUS_SUCCESS
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#define STATUS_SUCCESS 0
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#endif
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#define STATUS_FAIL 1
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#define STATUS_READ_FAIL 2
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#define STATUS_WRITE_FAIL 3
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#define STATUS_TIMEDOUT 4
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#define STATUS_NOMEM 5
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#define STATUS_TRANS_SHORT 6
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#define STATUS_TRANS_LONG 7
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#define STATUS_STALLED 8
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#define STATUS_ERROR 10
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#define IDLE_MAX_COUNT 10
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#define POLLING_WAIT_CNT 1
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#define DELINK_DELAY 100
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#define LED_TOGGLE_INTERVAL 6
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#define LED_GPIO 0
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/* package */
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#define QFN24 0
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#define LQFP48 1
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#define USB_11 0
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#define USB_20 1
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/*
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* Transport return codes
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*/
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/* Transport good, command good */
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#define TRANSPORT_GOOD 0
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/* Transport good, command failed */
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#define TRANSPORT_FAILED 1
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/* Command failed, no auto-sense */
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#define TRANSPORT_NO_SENSE 2
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/* Transport bad (i.e. device dead) */
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#define TRANSPORT_ERROR 3
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/* Supported Clock */
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enum card_clock { CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, CLK_80, CLK_100 };
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#ifdef _MSG_TRACE
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#define TRACE_ITEM_CNT 64
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struct trace_msg_t {
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u16 line;
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#define MSG_FUNC_LEN 64
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char func[MSG_FUNC_LEN];
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#define MSG_FILE_LEN 32
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char file[MSG_FILE_LEN];
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#define TIME_VAL_LEN 16
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u8 timeval_buf[TIME_VAL_LEN];
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u8 valid;
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};
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#endif /* _MSG_TRACE */
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/* Size of the autosense data buffer */
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#define SENSE_SIZE 18
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/* Sense type */
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#define SENSE_TYPE_NO_SENSE 0
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#define SENSE_TYPE_MEDIA_CHANGE 1
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#define SENSE_TYPE_MEDIA_NOT_PRESENT 2
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#define SENSE_TYPE_MEDIA_LBA_OVER_RANGE 3
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#define SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT 4
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#define SENSE_TYPE_MEDIA_WRITE_PROTECT 5
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#define SENSE_TYPE_MEDIA_INVALID_CMD_FIELD 6
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#define SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR 7
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#define SENSE_TYPE_MEDIA_WRITE_ERR 8
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#define SENSE_TYPE_FORMAT_IN_PROGRESS 9
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#define SENSE_TYPE_FORMAT_CMD_FAILED 10
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#ifdef SUPPORT_MAGIC_GATE
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/* COPY PROTECTION KEY EXCHANGE FAILURE - KEY NOT ESTABLISHED */
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#define SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB 0x0b
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/* COPY PROTECTION KEY EXCHANGE FAILURE - AUTHENTICATION FAILURE */
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#define SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN 0x0c
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/* INCOMPATIBLE MEDIUM INSTALLED */
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#define SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM 0x0d
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/* WRITE ERROR */
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#define SENSE_TYPE_MG_WRITE_ERR 0x0e
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#endif
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#ifdef SUPPORT_SD_LOCK
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/* FOR Locked SD card */
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#define SENSE_TYPE_MEDIA_READ_FORBIDDEN 0x10
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#endif
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/*---- sense key ----*/
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#define ILI 0x20 /* ILI bit is on */
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#define NO_SENSE 0x00 /* not exist sense key */
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#define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */
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#define NOT_READY 0x02 /* Logical unit is not ready */
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#define MEDIA_ERR 0x03 /* medium/data error */
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#define HARDWARE_ERR 0x04 /* hardware error */
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#define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */
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#define UNIT_ATTENTION 0x06 /* unit attention condition occur */
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#define DAT_PRTCT 0x07 /* read/write is desable */
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#define BLNC_CHK 0x08 /* find blank/DOF in read */
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/* write to unblank area */
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#define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illgal */
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#define ABRT_CMD 0x0b /* Target make the command in error */
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#define EQUAL 0x0c /* Search Data end with Equal */
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#define VLM_OVRFLW 0x0d /* Some data are left in buffer */
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#define MISCMP 0x0e /* find inequality */
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/*-----------------------------------
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SENSE_DATA
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-----------------------------------*/
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/*---- valid ----*/
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#define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */
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#define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */
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/*---- error code ----*/
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#define CUR_ERR 0x70 /* current error */
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#define DEF_ERR 0x71 /* specific command error */
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/*---- sense key Infomation ----*/
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#define SNSKEYINFO_LEN 3 /* length of sense key infomation */
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#define SKSV 0x80
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#define CDB_ILLEGAL 0x40
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#define DAT_ILLEGAL 0x00
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#define BPV 0x08
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#define BIT_ILLEGAL0 0 /* bit0 is illegal */
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#define BIT_ILLEGAL1 1 /* bit1 is illegal */
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#define BIT_ILLEGAL2 2 /* bit2 is illegal */
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#define BIT_ILLEGAL3 3 /* bit3 is illegal */
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#define BIT_ILLEGAL4 4 /* bit4 is illegal */
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#define BIT_ILLEGAL5 5 /* bit5 is illegal */
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#define BIT_ILLEGAL6 6 /* bit6 is illegal */
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#define BIT_ILLEGAL7 7 /* bit7 is illegal */
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/*---- ASC ----*/
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#define ASC_NO_INFO 0x00
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#define ASC_MISCMP 0x1d
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#define ASC_INVLD_CDB 0x24
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#define ASC_INVLD_PARA 0x26
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#define ASC_LU_NOT_READY 0x04
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#define ASC_WRITE_ERR 0x0c
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#define ASC_READ_ERR 0x11
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#define ASC_LOAD_EJCT_ERR 0x53
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#define ASC_MEDIA_NOT_PRESENT 0x3A
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#define ASC_MEDIA_CHANGED 0x28
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#define ASC_MEDIA_IN_PROCESS 0x04
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#define ASC_WRITE_PROTECT 0x27
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#define ASC_LUN_NOT_SUPPORTED 0x25
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/*---- ASQC ----*/
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#define ASCQ_NO_INFO 0x00
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#define ASCQ_MEDIA_IN_PROCESS 0x01
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#define ASCQ_MISCMP 0x00
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#define ASCQ_INVLD_CDB 0x00
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#define ASCQ_INVLD_PARA 0x02
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#define ASCQ_LU_NOT_READY 0x02
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#define ASCQ_WRITE_ERR 0x02
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#define ASCQ_READ_ERR 0x00
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#define ASCQ_LOAD_EJCT_ERR 0x00
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#define ASCQ_WRITE_PROTECT 0x00
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struct sense_data_t {
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unsigned char err_code; /* error code */
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/* bit7 : valid */
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/* (1 : SCSI2) */
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/* (0 : Vendor specific) */
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/* bit6-0 : error code */
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/* (0x70 : current error) */
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/* (0x71 : specific command error) */
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unsigned char seg_no; /* segment No. */
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unsigned char sense_key; /* byte5 : ILI */
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/* bit3-0 : sense key */
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unsigned char info[4]; /* infomation */
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unsigned char ad_sense_len; /* additional sense data length */
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unsigned char cmd_info[4]; /* command specific infomation */
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unsigned char asc; /* ASC */
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unsigned char ascq; /* ASCQ */
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unsigned char rfu; /* FRU */
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unsigned char sns_key_info[3]; /* sense key specific infomation */
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};
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/* sd_ctl bit map */
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/* SD push point control, bit 0, 1 */
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#define SD_PUSH_POINT_CTL_MASK 0x03
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#define SD_PUSH_POINT_DELAY 0x01
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#define SD_PUSH_POINT_AUTO 0x02
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/* SD sample point control, bit 2, 3 */
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#define SD_SAMPLE_POINT_CTL_MASK 0x0C
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#define SD_SAMPLE_POINT_DELAY 0x04
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#define SD_SAMPLE_POINT_AUTO 0x08
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/* SD DDR Tx phase set by user, bit 4 */
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#define SD_DDR_TX_PHASE_SET_BY_USER 0x10
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/* MMC DDR Tx phase set by user, bit 5 */
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#define MMC_DDR_TX_PHASE_SET_BY_USER 0x20
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/* Support MMC DDR mode, bit 6 */
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/*#define SUPPORT_MMC_DDR_MODE 0x40 */
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#define SUPPORT_UHS50_MMC44 0x40
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struct rts51x_option {
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u8 led_blink_speed;
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int mspro_formatter_enable;
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/* card clock expected by user for fpga platform */
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int fpga_sd_sdr104_clk;
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int fpga_sd_ddr50_clk;
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int fpga_sd_sdr50_clk;
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int fpga_sd_hs_clk;
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int fpga_mmc_52m_clk;
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int fpga_ms_hg_clk;
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int fpga_ms_4bit_clk;
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/* card clock expected by user for asic platform */
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int asic_sd_sdr104_clk;
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int asic_sd_ddr50_clk;
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int asic_sd_sdr50_clk;
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int asic_sd_hs_clk;
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int asic_mmc_52m_clk;
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int asic_ms_hg_clk;
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int asic_ms_4bit_clk;
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u8 ssc_depth_sd_sdr104; /* sw */
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u8 ssc_depth_sd_ddr50; /* sw */
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u8 ssc_depth_sd_sdr50; /* sw */
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u8 ssc_depth_sd_hs; /* sw */
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u8 ssc_depth_mmc_52m; /* sw */
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u8 ssc_depth_ms_hg; /* sw */
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u8 ssc_depth_ms_4bit; /* sw */
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u8 ssc_depth_low_speed; /* sw */
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/* SD/MMC Tx phase */
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int sd_ddr_tx_phase; /* Enabled by bit 4 of sd_ctl */
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int mmc_ddr_tx_phase; /* Enabled by bit 5 of sd_ctl */
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/* priority of choosing sd speed funciton */
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u32 sd_speed_prior;
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/* sd card control */
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u32 sd_ctl;
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/* Enable Selective Suspend */
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int ss_en;
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/* Interval to enter SS from IDLE state (second) */
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int ss_delay;
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int needs_remote_wakeup;
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u8 ww_enable; /* sangdy2010-08-03:add for remote wakeup */
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/* Enable SSC clock */
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int ssc_en;
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int auto_delink_en;
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/* sangdy2010-07-13:add FT2 fast mode */
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int FT2_fast_mode;
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/* sangdy2010-07-15:
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* add for config delay between 1/4 PMOS and 3/4 PMOS */
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int pwr_delay;
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int xd_rw_step; /* add to tune xd tRP */
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int D3318_off_delay; /* add to tune D3318 off delay time */
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int delink_delay; /* add to tune delink delay time */
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/* add for rts5129 to enable/disable D3318 off */
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u8 rts5129_D3318_off_enable;
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u8 sd20_pad_drive; /* add to config SD20 PAD drive */
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u8 sd30_pad_drive; /* add to config SD30 pad drive */
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/*if reset or rw fail,then set SD20 pad drive again */
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u8 reset_or_rw_fail_set_pad_drive;
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u8 rcc_fail_flag; /* add to indicate whether rcc bug happen */
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u8 rcc_bug_fix_en; /* if set,then support fixing rcc bug */
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u8 debounce_num; /* debounce number */
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int polling_time; /* polling delay time */
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u8 led_toggle_interval; /* used to control led toggle speed */
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int xd_rwn_step;
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u8 sd_send_status_en;
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/* used to store default phase which is
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* used when phase tune all pass. */
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u8 ddr50_tx_phase;
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u8 ddr50_rx_phase;
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u8 sdr50_tx_phase;
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u8 sdr50_rx_phase;
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/* used to enable select sdr50 tx phase according to proportion. */
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u8 sdr50_phase_sel;
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u8 ms_errreg_fix;
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u8 reset_mmc_first;
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u8 speed_mmc; /* when set, then try CMD55 only twice */
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u8 led_always_on; /* if set, then led always on when card exist */
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u8 dv18_voltage; /* add to tune dv18 voltage */
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};
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#define MS_FORMATTER_ENABLED(chip) ((chip)->option.mspro_formatter_enable)
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struct rts51x_chip;
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typedef int (*card_rw_func) (struct scsi_cmnd *srb, struct rts51x_chip *chip,
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u32 sec_addr, u16 sec_cnt);
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/* For MS Card */
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#define MAX_DEFECTIVE_BLOCK 10
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struct zone_entry {
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u16 *l2p_table;
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u16 *free_table;
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u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */
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int set_index;
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int get_index;
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int unused_blk_cnt;
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int disable_count;
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/* To indicate whether the L2P table of this zone has been built. */
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int build_flag;
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};
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struct xd_delay_write_tag {
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u32 old_phyblock;
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u32 new_phyblock;
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u32 logblock;
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u8 pageoff;
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u8 delay_write_flag;
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};
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struct xd_info {
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u8 maker_code;
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u8 device_code;
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u8 block_shift;
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u8 page_off;
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u8 addr_cycle;
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u16 cis_block;
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u8 multi_flag;
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u8 err_code;
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u32 capacity;
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struct zone_entry *zone;
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int zone_cnt;
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struct xd_delay_write_tag delay_write;
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int counter;
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int xd_clock;
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};
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#define TYPE_SD 0x0000
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#define TYPE_MMC 0x0001
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/* TYPE_SD */
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#define SD_HS 0x0100
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#define SD_SDR50 0x0200
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#define SD_DDR50 0x0400
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#define SD_SDR104 0x0800
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#define SD_HCXC 0x1000
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/* TYPE_MMC */
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#define MMC_26M 0x0100
|
|
#define MMC_52M 0x0200
|
|
#define MMC_4BIT 0x0400
|
|
#define MMC_8BIT 0x0800
|
|
#define MMC_SECTOR_MODE 0x1000
|
|
#define MMC_DDR52 0x2000
|
|
|
|
/* SD card */
|
|
#define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD)
|
|
#define CHK_SD_HS(sd_card) \
|
|
(CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS))
|
|
#define CHK_SD_SDR50(sd_card) \
|
|
(CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50))
|
|
#define CHK_SD_DDR50(sd_card) \
|
|
(CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50))
|
|
#define CHK_SD_SDR104(sd_card) \
|
|
(CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104))
|
|
#define CHK_SD_HCXC(sd_card) \
|
|
(CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC))
|
|
#define CHK_SD30_SPEED(sd_card) \
|
|
(CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) ||\
|
|
CHK_SD_SDR104(sd_card))
|
|
|
|
#define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD)
|
|
#define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS)
|
|
#define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50)
|
|
#define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50)
|
|
#define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104)
|
|
#define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC)
|
|
|
|
#define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS)
|
|
#define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50)
|
|
#define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50)
|
|
#define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104)
|
|
#define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC)
|
|
#define CLR_SD30_SPEED(sd_card) \
|
|
((sd_card)->sd_type &= ~(SD_SDR50|SD_DDR50|SD_SDR104))
|
|
|
|
/* MMC card */
|
|
#define CHK_MMC(sd_card) \
|
|
(((sd_card)->sd_type & 0xFF) == TYPE_MMC)
|
|
#define CHK_MMC_26M(sd_card) \
|
|
(CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M))
|
|
#define CHK_MMC_52M(sd_card) \
|
|
(CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M))
|
|
#define CHK_MMC_4BIT(sd_card) \
|
|
(CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT))
|
|
#define CHK_MMC_8BIT(sd_card) \
|
|
(CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT))
|
|
#define CHK_MMC_SECTOR_MODE(sd_card)\
|
|
(CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE))
|
|
#define CHK_MMC_DDR52(sd_card) \
|
|
(CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52))
|
|
|
|
#define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC)
|
|
#define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M)
|
|
#define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M)
|
|
#define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT)
|
|
#define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT)
|
|
#define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE)
|
|
#define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52)
|
|
|
|
#define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M)
|
|
#define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M)
|
|
#define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT)
|
|
#define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT)
|
|
#define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
|
|
#define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52)
|
|
|
|
#define CHK_MMC_HS(sd_card) \
|
|
(CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card))
|
|
#define CLR_MMC_HS(sd_card) \
|
|
do { \
|
|
CLR_MMC_DDR52(sd_card); \
|
|
CLR_MMC_52M(sd_card); \
|
|
CLR_MMC_26M(sd_card); \
|
|
} while (0)
|
|
|
|
#define SD_SUPPORT_CLASS_TEN 0x01
|
|
#define SD_SUPPORT_1V8 0x02
|
|
|
|
#define SD_SET_CLASS_TEN(sd_card) \
|
|
((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN)
|
|
#define SD_CHK_CLASS_TEN(sd_card) \
|
|
((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN)
|
|
#define SD_CLR_CLASS_TEN(sd_card) \
|
|
((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN)
|
|
#define SD_SET_1V8(sd_card) \
|
|
((sd_card)->sd_setting |= SD_SUPPORT_1V8)
|
|
#define SD_CHK_1V8(sd_card) \
|
|
((sd_card)->sd_setting & SD_SUPPORT_1V8)
|
|
#define SD_CLR_1V8(sd_card) \
|
|
((sd_card)->sd_setting &= ~SD_SUPPORT_1V8)
|
|
#define CLR_RETRY_SD20_MODE(sd_card) \
|
|
((sd_card)->retry_SD20_mode = 0)
|
|
#define SET_RETRY_SD20_MODE(sd_card) \
|
|
((sd_card)->retry_SD20_mode = 1)
|
|
#define CHK_RETRY_SD20_MODE(sd_card) \
|
|
((sd_card)->retry_SD20_mode == 1)
|
|
|
|
struct sd_info {
|
|
u16 sd_type;
|
|
u8 err_code;
|
|
u8 sd_data_buf_ready;
|
|
u32 sd_addr;
|
|
u32 capacity;
|
|
|
|
u8 raw_csd[16];
|
|
u8 raw_scr[8];
|
|
|
|
/* Sequential RW */
|
|
int seq_mode;
|
|
enum dma_data_direction pre_dir;
|
|
u32 pre_sec_addr;
|
|
u16 pre_sec_cnt;
|
|
|
|
int counter;
|
|
|
|
int sd_clock;
|
|
|
|
#ifdef SUPPORT_CPRM
|
|
int sd_pass_thru_en;
|
|
int pre_cmd_err;
|
|
u8 last_rsp_type;
|
|
u8 rsp[17];
|
|
#endif
|
|
|
|
u8 func_group1_mask;
|
|
u8 func_group2_mask;
|
|
u8 func_group3_mask;
|
|
u8 func_group4_mask;
|
|
|
|
u8 sd_switch_fail;
|
|
u8 sd_read_phase;
|
|
u8 retry_SD20_mode; /* sangdy2010-06-10 */
|
|
u8 sd_reset_fail; /* sangdy2010-07-01 */
|
|
u8 sd_send_status_en;
|
|
|
|
#ifdef SUPPORT_SD_LOCK
|
|
u8 sd_lock_status;
|
|
u8 sd_erase_status;
|
|
u8 sd_lock_notify;
|
|
#endif
|
|
};
|
|
|
|
#define MODE_512_SEQ 0x01
|
|
#define MODE_2K_SEQ 0x02
|
|
|
|
#define TYPE_MS 0x0000
|
|
#define TYPE_MSPRO 0x0001
|
|
|
|
#define MS_4BIT 0x0100
|
|
#define MS_8BIT 0x0200
|
|
#define MS_HG 0x0400
|
|
#define MS_XC 0x0800
|
|
|
|
#define HG8BIT (MS_HG | MS_8BIT)
|
|
|
|
#define CHK_MSPRO(ms_card) \
|
|
(((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
|
|
#define CHK_HG8BIT(ms_card) \
|
|
(CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT))
|
|
#define CHK_MSXC(ms_card) \
|
|
(CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC))
|
|
#define CHK_MSHG(ms_card) \
|
|
(CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG))
|
|
|
|
#define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT))
|
|
#define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT))
|
|
|
|
struct ms_delay_write_tag {
|
|
u16 old_phyblock;
|
|
u16 new_phyblock;
|
|
u16 logblock;
|
|
u8 pageoff;
|
|
u8 delay_write_flag;
|
|
};
|
|
|
|
struct ms_info {
|
|
u16 ms_type;
|
|
u8 block_shift;
|
|
u8 page_off;
|
|
u16 total_block;
|
|
u16 boot_block;
|
|
u32 capacity;
|
|
|
|
u8 check_ms_flow;
|
|
u8 switch_8bit_fail;
|
|
u8 err_code;
|
|
|
|
struct zone_entry *segment;
|
|
int segment_cnt;
|
|
|
|
int pro_under_formatting;
|
|
int format_status;
|
|
u16 progress;
|
|
u8 raw_sys_info[96];
|
|
#ifdef SUPPORT_PCGL_1P18
|
|
u8 raw_model_name[48];
|
|
#endif
|
|
|
|
u8 multi_flag;
|
|
|
|
/* Sequential RW */
|
|
u8 seq_mode;
|
|
enum dma_data_direction pre_dir;
|
|
u32 pre_sec_addr;
|
|
u16 pre_sec_cnt;
|
|
u32 total_sec_cnt;
|
|
u8 last_rw_int;
|
|
|
|
struct ms_delay_write_tag delay_write;
|
|
|
|
int counter;
|
|
|
|
int ms_clock;
|
|
|
|
#ifdef SUPPORT_MAGIC_GATE
|
|
u8 magic_gate_id[16];
|
|
u8 mg_entry_num;
|
|
int mg_auth; /* flag to indicate authentication process */
|
|
#endif
|
|
};
|
|
|
|
#define PRO_UNDER_FORMATTING(ms_card) \
|
|
((ms_card)->pro_under_formatting)
|
|
#define SET_FORMAT_STATUS(ms_card, status) \
|
|
((ms_card)->format_status = (status))
|
|
#define CHK_FORMAT_STATUS(ms_card, status) \
|
|
((ms_card)->format_status == (status))
|
|
|
|
struct scsi_cmnd;
|
|
|
|
enum CHIP_STAT { STAT_INIT, STAT_IDLE, STAT_RUN, STAT_SS_PRE, STAT_SS,
|
|
STAT_SUSPEND };
|
|
|
|
struct rts51x_chip {
|
|
u16 vendor_id;
|
|
u16 product_id;
|
|
char max_lun;
|
|
|
|
struct scsi_cmnd *srb;
|
|
struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT];
|
|
|
|
#ifndef LED_AUTO_BLINK
|
|
int led_toggle_counter;
|
|
#endif
|
|
int ss_counter;
|
|
int idle_counter;
|
|
int auto_delink_counter;
|
|
enum CHIP_STAT chip_stat;
|
|
|
|
int resume_from_scsi;
|
|
|
|
/* Card information */
|
|
struct xd_info xd_card;
|
|
struct sd_info sd_card;
|
|
struct ms_info ms_card;
|
|
|
|
int cur_clk; /* current card clock */
|
|
int cur_card; /* Current card module */
|
|
|
|
u8 card_exist; /* card exist bit map (physical exist) */
|
|
u8 card_ready; /* card ready bit map (reset successfully) */
|
|
u8 card_fail; /* card reset fail bit map */
|
|
u8 card_ejected; /* card ejected bit map */
|
|
u8 card_wp; /* card write protected bit map */
|
|
|
|
u8 fake_card_ready;
|
|
/* flag to indicate whether to answer MediaChange */
|
|
unsigned long lun_mc;
|
|
|
|
/* card bus width */
|
|
u8 card_bus_width[MAX_ALLOWED_LUN_CNT];
|
|
/* card capacity */
|
|
u32 capacity[MAX_ALLOWED_LUN_CNT];
|
|
|
|
/* read/write card function pointer */
|
|
card_rw_func rw_card[MAX_ALLOWED_LUN_CNT];
|
|
/* read/write capacity, used for GPIO Toggle */
|
|
u32 rw_cap[MAX_ALLOWED_LUN_CNT];
|
|
/* card to lun mapping table */
|
|
u8 card2lun[32];
|
|
/* lun to card mapping table */
|
|
u8 lun2card[MAX_ALLOWED_LUN_CNT];
|
|
|
|
#ifdef _MSG_TRACE
|
|
struct trace_msg_t trace_msg[TRACE_ITEM_CNT];
|
|
int msg_idx;
|
|
#endif
|
|
|
|
int rw_need_retry;
|
|
|
|
/* ASIC or FPGA */
|
|
int asic_code;
|
|
|
|
/* QFN24 or LQFP48 */
|
|
int package;
|
|
|
|
/* Full Speed or High Speed */
|
|
int usb_speed;
|
|
|
|
/*sangdy:enable or disable UHS50 and MMC4.4 */
|
|
int uhs50_mmc44_en;
|
|
|
|
u8 ic_version;
|
|
|
|
/* Command buffer */
|
|
u8 *cmd_buf;
|
|
unsigned int cmd_idx;
|
|
/* Response buffer */
|
|
u8 *rsp_buf;
|
|
|
|
u16 card_status;
|
|
|
|
#ifdef SUPPORT_OCP
|
|
u16 ocp_stat;
|
|
#endif
|
|
|
|
struct rts51x_option option;
|
|
struct rts51x_usb *usb;
|
|
|
|
u8 rcc_read_response;
|
|
int reset_need_retry;
|
|
u8 rts5179;
|
|
};
|
|
|
|
#define UHS50_EN 0x0001
|
|
#define UHS50_DIS 0x0000
|
|
#define SET_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_EN)
|
|
#define CLEAR_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_DIS)
|
|
#define CHECK_UHS50(chip) (((chip)->uhs50_mmc44_en&0xff) == UHS50_EN)
|
|
|
|
#define RTS51X_GET_VID(chip) ((chip)->vendor_id)
|
|
#define RTS51X_GET_PID(chip) ((chip)->product_id)
|
|
|
|
#define RTS51X_SET_STAT(chip, stat) \
|
|
do { \
|
|
if ((stat) != STAT_IDLE) { \
|
|
(chip)->idle_counter = 0; \
|
|
} \
|
|
(chip)->chip_stat = (enum CHIP_STAT)(stat); \
|
|
} while (0)
|
|
#define RTS51X_CHK_STAT(chip, stat) ((chip)->chip_stat == (stat))
|
|
#define RTS51X_GET_STAT(chip) ((chip)->chip_stat)
|
|
|
|
#define CHECK_PID(chip, pid) (RTS51X_GET_PID(chip) == (pid))
|
|
#define CHECK_PKG(chip, pkg) ((chip)->package == (pkg))
|
|
#define CHECK_USB(chip, speed) ((chip)->usb_speed == (speed))
|
|
|
|
int rts51x_reset_chip(struct rts51x_chip *chip);
|
|
int rts51x_init_chip(struct rts51x_chip *chip);
|
|
int rts51x_release_chip(struct rts51x_chip *chip);
|
|
void rts51x_polling_func(struct rts51x_chip *chip);
|
|
|
|
static inline void rts51x_init_cmd(struct rts51x_chip *chip)
|
|
{
|
|
chip->cmd_idx = 0;
|
|
chip->cmd_buf[0] = 'R';
|
|
chip->cmd_buf[1] = 'T';
|
|
chip->cmd_buf[2] = 'C';
|
|
chip->cmd_buf[3] = 'R';
|
|
chip->cmd_buf[PACKET_TYPE] = BATCH_CMD;
|
|
}
|
|
|
|
void rts51x_add_cmd(struct rts51x_chip *chip,
|
|
u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
|
|
int rts51x_send_cmd(struct rts51x_chip *chip, u8 flag, int timeout);
|
|
int rts51x_get_rsp(struct rts51x_chip *chip, int rsp_len, int timeout);
|
|
|
|
static inline void rts51x_read_rsp_buf(struct rts51x_chip *chip, int offset,
|
|
u8 *buf, int buf_len)
|
|
{
|
|
memcpy(buf, chip->rsp_buf + offset, buf_len);
|
|
}
|
|
|
|
static inline u8 *rts51x_get_rsp_data(struct rts51x_chip *chip)
|
|
{
|
|
return chip->rsp_buf;
|
|
}
|
|
|
|
int rts51x_get_card_status(struct rts51x_chip *chip, u16 *status);
|
|
int rts51x_write_register(struct rts51x_chip *chip, u16 addr, u8 mask, u8 data);
|
|
int rts51x_read_register(struct rts51x_chip *chip, u16 addr, u8 *data);
|
|
int rts51x_ep0_write_register(struct rts51x_chip *chip, u16 addr, u8 mask,
|
|
u8 data);
|
|
int rts51x_ep0_read_register(struct rts51x_chip *chip, u16 addr, u8 *data);
|
|
int rts51x_seq_write_register(struct rts51x_chip *chip, u16 addr, u16 len,
|
|
u8 *data);
|
|
int rts51x_seq_read_register(struct rts51x_chip *chip, u16 addr, u16 len,
|
|
u8 *data);
|
|
int rts51x_read_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len);
|
|
int rts51x_write_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len);
|
|
int rts51x_write_phy_register(struct rts51x_chip *chip, u8 addr, u8 val);
|
|
int rts51x_read_phy_register(struct rts51x_chip *chip, u8 addr, u8 *val);
|
|
void rts51x_do_before_power_down(struct rts51x_chip *chip);
|
|
void rts51x_clear_hw_error(struct rts51x_chip *chip);
|
|
void rts51x_prepare_run(struct rts51x_chip *chip);
|
|
void rts51x_trace_msg(struct rts51x_chip *chip, unsigned char *buf, int clear);
|
|
void rts51x_pp_status(struct rts51x_chip *chip, unsigned int lun, u8 *status,
|
|
u8 status_len);
|
|
void rts51x_read_status(struct rts51x_chip *chip, unsigned int lun,
|
|
u8 *rts51x_status, u8 status_len);
|
|
int rts51x_transfer_data_rcc(struct rts51x_chip *chip, unsigned int pipe,
|
|
void *buf, unsigned int len, int use_sg,
|
|
unsigned int *act_len, int timeout, u8 stage_flag);
|
|
|
|
#define RTS51X_WRITE_REG(chip, addr, mask, data) \
|
|
do { \
|
|
int _retval = rts51x_write_register((chip), \
|
|
(addr), (mask), (data)); \
|
|
if (_retval != STATUS_SUCCESS) { \
|
|
TRACE_RET((chip), _retval); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define RTS51X_READ_REG(chip, addr, data) \
|
|
do { \
|
|
int _retval = rts51x_read_register((chip), \
|
|
(addr), (data)); \
|
|
if (_retval != STATUS_SUCCESS) { \
|
|
TRACE_RET((chip), _retval); \
|
|
} \
|
|
} while (0)
|
|
|
|
#endif /* __RTS51X_CHIP_H */
|