6d45a4028c
This patch adds cpuidle support for i.MX7ULP, 3 cpuidle states supported as below: 1. WFI, just ARM wfi; 2. WAIT mode, mapped to SoC's partial stop mode #3; 3. STOP mode, mapped to SoC's partial stop mode #1. In WAIT mode, system clock and bus clock will be enabled; In STOP mode, system clock and bus clock will be disabled. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
61 lines
1.1 KiB
C
61 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Anson Huang <Anson.Huang@nxp.com>
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*/
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <asm/cpuidle.h>
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#include "common.h"
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#include "cpuidle.h"
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static int imx7ulp_enter_wait(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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if (index == 1)
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imx7ulp_set_lpm(ULP_PM_WAIT);
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else
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imx7ulp_set_lpm(ULP_PM_STOP);
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cpu_do_idle();
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imx7ulp_set_lpm(ULP_PM_RUN);
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return index;
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}
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static struct cpuidle_driver imx7ulp_cpuidle_driver = {
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.name = "imx7ulp_cpuidle",
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.owner = THIS_MODULE,
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.states = {
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/* WFI */
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ARM_CPUIDLE_WFI_STATE,
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/* WAIT */
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{
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.exit_latency = 50,
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.target_residency = 75,
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.enter = imx7ulp_enter_wait,
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.name = "WAIT",
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.desc = "PSTOP2",
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},
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/* STOP */
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{
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.exit_latency = 100,
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.target_residency = 150,
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.enter = imx7ulp_enter_wait,
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.name = "STOP",
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.desc = "PSTOP1",
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},
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},
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.state_count = 3,
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.safe_state_index = 0,
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};
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int __init imx7ulp_cpuidle_init(void)
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{
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return cpuidle_register(&imx7ulp_cpuidle_driver, NULL);
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}
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