a1a0db36d8
These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. This includes two branches for arm64 dt updates, both following up on earlier changes for the same platforms that are already merged: Samsung: - add USB3 support in Exynos7 - minor PM related updates Amlogic: - new machines: WeTek Set-top-boxes - various devices added to DT There are also a couple of bugfixes that trickled in since the start of the merge window: - The moxart_defconfig was not building the intended platform - CPU-hotplug was broken on ux500 - Coresight was broken on Juno (never worked) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAWLmRS2CrR//JCVInAQKrkQ//bd8TCGXA0tRwDMEGejtWChZcNkGZDaer sNMyE/c1p5+/4euSmf3jW1JsIx4JDtjr0psKeRpgYId8GVdvaYceFbSMJl6o9hDc pm3sqb66xEgrWQoSBA2Urz/RhSIrxkYbuTpYbN4teV9I/IFgTUggaBSzfkq3SLRE bEVSbCw0S/6t3vJgW4CKCI75+a3NexqImvi8txNwueQQMnDLnOkG97vMUQJgDq0j E+CeOk0mvlGF+TiVoAhUxT3YIt8azUTfUVw7CBIRvo/49sUCiETk6xie93FaC7GI Tmg9KK+oZhrmqt8PBGkikxQMHATnKrfJbMNi/K6nrxW91ylSkwTN/7jfhSjFDrdI 4WNB2x3u6KUnQ0XOKVY36gUnV8kJ/2K9pTZpq0K7m4czo8YAid9LumvDnqhPI0Xg fXxq3YBx7AfzsdBL3+nQ7AH3tr9Bvt01kMZwYwNgpqtglEBScAgzyrPG/yyTBFq7 KOkoyNojTaHZHcDtYqSaxYls+2tdeyvYuQJ7QGQ5DJCW99NgbRuFfIUJvgwRPoKt 13ioIJxDUHmemR6xFURWVH1dPkkqwtJht7us5jcxuxBL9ZhmEb6vophvyxj62zTZ 8A+PE3cC1azhKph7rVrUl9KEoYZzedwDaTGBNpYz1gN7DxDvWHYINEPB4bBLzYmv uWsSYVbV2Qs= =A3U6 -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. This includes two branches for arm64 dt updates, both following up on earlier changes for the same platforms that are already merged: Samsung: - add USB3 support in Exynos7 - minor PM related updates Amlogic: - new machines: WeTek Set-top-boxes - various devices added to DT There are also a couple of bugfixes that trickled in since the start of the merge window: - The moxart_defconfig was not building the intended platform - CPU-hotplug was broken on ux500 - Coresight was broken on Juno (never worked)" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: deconfig: fix the moxart defconfig ARM: ux500: resume the second core properly arm64: dts: juno: update definition for programmable replicator arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ...
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
/*
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* Copyright (C) 2002 ARM Ltd.
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* Copyright (C) 2008 STMicroelctronics.
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* Copyright (C) 2009 ST-Ericsson.
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* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
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*
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* This file is based on arm realview platform
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "db8500-regs.h"
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/* Magic triggers in backup RAM */
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#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
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#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
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static void __iomem *backupram;
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static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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static void __iomem *scu_base;
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unsigned int ncores;
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int i;
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np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
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if (!np) {
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pr_err("No backupram base address\n");
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return;
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}
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backupram = of_iomap(np, 0);
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of_node_put(np);
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if (!backupram) {
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pr_err("No backupram remap\n");
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return;
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}
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!np) {
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pr_err("No SCU base address\n");
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return;
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}
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scu_base = of_iomap(np, 0);
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of_node_put(np);
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if (!scu_base) {
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pr_err("No SCU remap\n");
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return;
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}
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scu_enable(scu_base);
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ncores = scu_get_core_count(scu_base);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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iounmap(scu_base);
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}
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static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/*
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* write the address of secondary startup into the backup ram register
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* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
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* backup ram register at offset 0x1FF0, which is what boot rom code
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* is waiting for. This will wake up the secondary core from WFE.
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*/
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writel(__pa_symbol(secondary_startup),
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backupram + UX500_CPU1_JUMPADDR_OFFSET);
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writel(0xA1FEED01,
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backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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mb();
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void ux500_cpu_die(unsigned int cpu)
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{
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wfi();
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}
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#endif
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static const struct smp_operations ux500_smp_ops __initconst = {
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.smp_prepare_cpus = ux500_smp_prepare_cpus,
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.smp_boot_secondary = ux500_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = ux500_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
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