![Oskar Schirmer](/assets/img/avatar_default.png)
There are four slightly different dma engines on the s6000 family. One for memory-memory transfers, the other three for memory-device. This patch implements a platform-specific kernel-API to control these engines. It is needed for the network, video, audio peripherals on s6000. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Daniel Glockner <dg@emlix.com> Signed-off-by: Fabian Godehardt <fg@emlix.com> Cc: Daniel Glockner <dg@emlix.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Chris Zankel <chris@zankel.net>
174 lines
4.7 KiB
C
174 lines
4.7 KiB
C
/*
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* Authors: Oskar Schirmer <os@emlix.com>
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* Daniel Gloeckner <dg@emlix.com>
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* (c) 2008 emlix GmbH http://www.emlix.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <asm/cacheflush.h>
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#include <variant/dmac.h>
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/* DMA engine lookup */
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struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
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/* DMA control, per engine */
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void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
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{
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if (xtensa_need_flush_dma_source(src)) {
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u32 base = src;
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u32 span = size;
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u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
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if (chunk && (size > chunk)) {
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s32 skip =
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readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
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u32 gaps = (size+chunk-1)/chunk - 1;
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if (skip >= 0) {
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span += gaps * skip;
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} else if (-skip > chunk) {
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s32 decr = gaps * (chunk + skip);
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base += decr;
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span = chunk - decr;
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} else {
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span = max(span + gaps * skip,
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(chunk + skip) * gaps - skip);
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}
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}
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flush_dcache_unaligned(base, span);
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}
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if (xtensa_need_invalidate_dma_destination(dst)) {
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u32 base = dst;
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u32 span = size;
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u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
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if (chunk && (size > chunk)) {
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s32 skip =
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readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
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u32 gaps = (size+chunk-1)/chunk - 1;
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if (skip >= 0) {
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span += gaps * skip;
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} else if (-skip > chunk) {
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s32 decr = gaps * (chunk + skip);
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base += decr;
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span = chunk - decr;
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} else {
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span = max(span + gaps * skip,
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(chunk + skip) * gaps - skip);
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}
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}
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invalidate_dcache_unaligned(base, span);
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}
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s6dmac_put_fifo(dmac, chan, src, dst, size);
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}
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void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
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{
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unsigned long flags;
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spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
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spin_lock_irqsave(spinl, flags);
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_s6dmac_disable_error_irqs(dmac, mask);
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spin_unlock_irqrestore(spinl, flags);
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}
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u32 s6dmac_int_sources(u32 dmac, u32 channel)
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{
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u32 mask, ret, tmp;
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mask = 1 << channel;
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tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
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tmp &= mask;
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writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
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ret = tmp >> channel;
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tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
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tmp &= mask;
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writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
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ret |= (tmp >> channel) << 1;
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tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
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tmp &= mask;
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writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
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ret |= (tmp >> channel) << 2;
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tmp = readl(dmac + S6_DMA_INTRAW0);
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tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER);
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writel(tmp, dmac + S6_DMA_INTCLEAR0);
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if (tmp & (mask << S6_DMA_INT0_UNDER))
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ret |= 1 << 3;
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if (tmp & (mask << S6_DMA_INT0_OVER))
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ret |= 1 << 4;
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tmp = readl(dmac + S6_DMA_MASTERERRINFO);
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mask <<= S6_DMA_INT1_CHANNEL;
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if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
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== channel)
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mask |= 1 << S6_DMA_INT1_MASTER;
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if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
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== channel)
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mask |= 1 << (S6_DMA_INT1_MASTER + 1);
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if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
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== channel)
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mask |= 1 << (S6_DMA_INT1_MASTER + 2);
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tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
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writel(tmp, dmac + S6_DMA_INTCLEAR1);
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ret |= ((tmp >> channel) & 1) << 5;
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ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
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return ret;
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}
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void s6dmac_release_chan(u32 dmac, int chan)
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{
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if (chan >= 0)
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s6dmac_disable_chan(dmac, chan);
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}
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/* global init */
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static inline void __init dmac_init(u32 dmac, u8 chan_nb)
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{
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s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
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spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
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s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
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writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
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dmac + S6_DMA_INTCLEAR1);
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}
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static inline void __init dmac_master(u32 dmac,
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u32 m0start, u32 m0end, u32 m1start, u32 m1end)
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{
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writel(m0start, dmac + S6_DMA_MASTER0START);
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writel(m0end - 1, dmac + S6_DMA_MASTER0END);
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writel(m1start, dmac + S6_DMA_MASTER1START);
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writel(m1end - 1, dmac + S6_DMA_MASTER1END);
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}
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static void __init s6_dmac_init(void)
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{
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dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);
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dmac_master(S6_REG_LMSDMA,
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S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC);
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dmac_init(S6_REG_NIDMA, S6_NIDMA_NB);
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dmac_init(S6_REG_DPDMA, S6_DPDMA_NB);
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dmac_master(S6_REG_DPDMA,
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S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA);
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dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB);
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dmac_master(S6_REG_HIFDMA,
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S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX);
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}
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arch_initcall(s6_dmac_init);
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