![Daniel Glöckner](/assets/img/avatar_default.png)
Implement an irq chip to handle interrupts via gpio. The GPIO chip initialization function now takes a bitmask denoting pins that should be configured for their alternate function. changes compared to v1: - fixed bug on edge interrupt configuration - accommodated to function name change - moved definition of VARIANT_NR_IRQS to this patch - renamed __XTENSA_S6000_IRQ_H to _XTENSA_S6000_IRQ_H as requested Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
232 lines
5.4 KiB
C
232 lines
5.4 KiB
C
/*
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* s6000 gpio driver
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*
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* Copyright (c) 2009 emlix GmbH
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* Authors: Oskar Schirmer <os@emlix.com>
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* Johannes Weiner <jw@emlix.com>
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* Daniel Gloeckner <dg@emlix.com>
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*/
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <variant/hardware.h>
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#define IRQ_BASE XTENSA_NR_IRQS
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#define S6_GPIO_DATA 0x000
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#define S6_GPIO_IS 0x404
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#define S6_GPIO_IBE 0x408
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#define S6_GPIO_IEV 0x40C
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#define S6_GPIO_IE 0x410
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#define S6_GPIO_RIS 0x414
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#define S6_GPIO_MIS 0x418
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#define S6_GPIO_IC 0x41C
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#define S6_GPIO_AFSEL 0x420
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#define S6_GPIO_DIR 0x800
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#define S6_GPIO_BANK(nr) ((nr) * 0x1000)
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#define S6_GPIO_MASK(nr) (4 << (nr))
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#define S6_GPIO_OFFSET(nr) \
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(S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
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static int direction_input(struct gpio_chip *chip, unsigned int off)
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{
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writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
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return 0;
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}
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static int get(struct gpio_chip *chip, unsigned int off)
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{
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return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
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}
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static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
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{
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unsigned rel = S6_GPIO_OFFSET(off);
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writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
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writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
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return 0;
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}
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static void set(struct gpio_chip *chip, unsigned int off, int val)
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{
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writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
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}
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static int to_irq(struct gpio_chip *chip, unsigned offset)
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{
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if (offset < 8)
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return offset + IRQ_BASE;
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return -EINVAL;
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}
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static struct gpio_chip gpiochip = {
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.owner = THIS_MODULE,
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.direction_input = direction_input,
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.get = get,
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.direction_output = direction_output,
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.set = set,
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.to_irq = to_irq,
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.base = 0,
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.ngpio = 24,
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.can_sleep = 0, /* no blocking io needed */
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.exported = 0, /* no exporting to userspace */
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};
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int s6_gpio_init(u32 afsel)
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{
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writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL);
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writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL);
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writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL);
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return gpiochip_add(&gpiochip);
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}
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static void ack(unsigned int irq)
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{
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writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
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}
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static void mask(unsigned int irq)
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{
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u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
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r &= ~(1 << (irq - IRQ_BASE));
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writeb(r, S6_REG_GPIO + S6_GPIO_IE);
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}
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static void unmask(unsigned int irq)
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{
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u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
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m |= 1 << (irq - IRQ_BASE);
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writeb(m, S6_REG_GPIO + S6_GPIO_IE);
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}
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static int set_type(unsigned int irq, unsigned int type)
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{
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const u8 m = 1 << (irq - IRQ_BASE);
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irq_flow_handler_t handler;
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struct irq_desc *desc;
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u8 reg;
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if (type == IRQ_TYPE_PROBE) {
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if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m)
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|| (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m)
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|| readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR
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+ S6_GPIO_MASK(irq - IRQ_BASE)))
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return 0;
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type = IRQ_TYPE_EDGE_BOTH;
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}
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reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
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reg |= m;
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handler = handle_level_irq;
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} else {
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reg &= ~m;
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handler = handle_edge_irq;
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}
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writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
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desc = irq_to_desc(irq);
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desc->handle_irq = handler;
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reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
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if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
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reg |= m;
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else
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reg &= ~m;
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writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
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reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
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if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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reg |= m;
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else
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reg &= ~m;
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writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
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return 0;
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}
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static struct irq_chip gpioirqs = {
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.name = "GPIO",
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.ack = ack,
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.mask = mask,
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.unmask = unmask,
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.set_type = set_type,
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};
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static u8 demux_masks[4];
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static void demux_irqs(unsigned int irq, struct irq_desc *desc)
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{
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u8 *mask = get_irq_desc_data(desc);
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u8 pending;
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int cirq;
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desc->chip->mask(irq);
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desc->chip->ack(irq);
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pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
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cirq = IRQ_BASE - 1;
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while (pending) {
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int n = ffs(pending);
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cirq += n;
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pending >>= n;
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generic_handle_irq(cirq);
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}
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desc->chip->unmask(irq);
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}
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extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
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void __init variant_init_irq(void)
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{
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int irq, n;
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writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE);
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for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) {
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const signed char *mapping = platform_irq_mappings[irq];
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int alone = 1;
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u8 mask;
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if (!mapping)
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continue;
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for(mask = 0; *mapping != -1; mapping++)
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switch (*mapping) {
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case S6_INTC_GPIO(0):
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mask |= 1 << 0;
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break;
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case S6_INTC_GPIO(1):
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mask |= 1 << 1;
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break;
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case S6_INTC_GPIO(2):
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mask |= 1 << 2;
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break;
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case S6_INTC_GPIO(3):
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mask |= 0x1f << 3;
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break;
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default:
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alone = 0;
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}
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if (mask) {
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int cirq, i;
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if (!alone) {
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printk(KERN_ERR "chained irq chips can't share"
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" parent irq %i\n", irq);
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continue;
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}
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demux_masks[n] = mask;
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cirq = IRQ_BASE - 1;
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do {
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i = ffs(mask);
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cirq += i;
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mask >>= i;
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set_irq_chip(cirq, &gpioirqs);
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set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
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} while (mask);
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set_irq_data(irq, demux_masks + n);
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set_irq_chained_handler(irq, demux_irqs);
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if (++n == ARRAY_SIZE(demux_masks))
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break;
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}
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}
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}
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