fc35c1966e
large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Core: - Runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - Runtime PM support for Samsung exynos5433/exynos4412 providers - Removal of clkdev aliases on Samsung SoCs - Convert clk-gpio to use gpio descriptors - Various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - Sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - Support for the second display unit clock on Renesas RZ/G1E - Suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - New clock ids for Rockchip rk3188 and rk3368 SoCs - Various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJaD3qRAAoJEK0CiJfG5JUlOLgQAKWekgG/IYgcPzPWDYfg8Hwr sVVUK7+q7TVfbHsbYVikJuUaxutKZ0onnrYmOalTTyyxqL2E1/rYScnxdYHfcwX8 cyfHebRHsbh/Xg45ktwjzBkO49nwuppkpXd/V80GSBUZ+lsIVl5DUrrFAZdRUEdr CEsAsF9tEWIl+0gqXYNuiKBV7QAYv5BUPrbJQf0PwL6jX0OAhLv+ukfN8BdmYsOb rdoqhdgmyHkTuIMqsC/H2yP59aAKBse7wxIYebDiTdbPWfTkC9q927fTs4A02F6L sHfLvCpfuB4rOjXy6LSd1gMGWIcjotZai+idHBqtNLLVz6exF1QpUCp+pZjEULbA /Sx9lk8A3cYoa8pTu1NrrZbZX17iHkFswqMF3T20nhUN9+Ti597ZEbRcWDcoEZtw v2NznOTJ7Mm2SrNHOvDklstggNIGcwiAEePGMo7rJNEQZChpDjQj/gJWKzn0UwL4 zfk+0EzoejPdvZ5FJUfmlr8Tqk53uw+y7/0xQ6gf8lDviTrzzoeXtJUyumGBiuGx RxFywf8n02oLYRJm5hu+0NkC+/bX0Lxg/kwiR6FLBFbBFgkWyp7FGcxhlm6ZiBfe 0KkPciWslNavn5KhljIkZDbXymbvhhSr9uBEFsyeJueA5q7sSghWloL8Ag1cac3W e6swD1ngXtM/t5gjOLhR =hC7z -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
256 lines
10 KiB
C
256 lines
10 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/stddef.h>
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#include "clk-uniphier.h"
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#define UNIPHIER_LD4_SYS_CLK_SD \
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UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
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UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
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#define UNIPHIER_PRO5_SYS_CLK_SD \
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UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
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UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
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#define UNIPHIER_LD20_SYS_CLK_SD \
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UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
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UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
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/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
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#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
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UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \
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UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
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#define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
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UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \
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UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
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#define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
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UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \
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UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0)
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#define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
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UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
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#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
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UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
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#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
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UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
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#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
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UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
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#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
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UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
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#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
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UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
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UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
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#define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
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UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
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UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
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#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
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UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
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UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
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#define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \
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UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
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#define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \
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UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
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const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
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UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
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UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
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UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
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UNIPHIER_LD4_SYS_CLK_NAND(2),
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UNIPHIER_LD4_SYS_CLK_SD,
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UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
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UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
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UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
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UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
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UNIPHIER_LD4_SYS_CLK_NAND(2),
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UNIPHIER_LD4_SYS_CLK_SD,
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UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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UNIPHIER_PRO4_SYS_CLK_ETHER(6),
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UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
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UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
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UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
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UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
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UNIPHIER_LD4_SYS_CLK_NAND(2),
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UNIPHIER_LD4_SYS_CLK_SD,
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UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
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UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
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UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
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UNIPHIER_PRO5_SYS_CLK_NAND(2),
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UNIPHIER_PRO5_SYS_CLK_SD,
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UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
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UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
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UNIPHIER_PRO5_SYS_CLK_NAND(2),
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UNIPHIER_PRO5_SYS_CLK_SD,
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UNIPHIER_PRO4_SYS_CLK_ETHER(6),
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UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
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/* GIO is always clock-enabled: no function for 0x2104 bit6 */
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
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/* The document mentions 0x2104 bit 18, but not functional */
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UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
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UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */
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UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
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UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_LD11_SYS_CLK_EMMC(4),
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/* Index 5 reserved for eMMC PHY */
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UNIPHIER_LD11_SYS_CLK_ETHER(6),
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UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
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UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
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UNIPHIER_LD11_SYS_CLK_AIO(40),
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UNIPHIER_LD11_SYS_CLK_EVEA(41),
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UNIPHIER_LD11_SYS_CLK_EXIV(42),
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/* CPU gears */
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UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
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UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
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UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
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/* Note: both gear1 and gear4 are spll/4. This is not a bug. */
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UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
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"cpll/2", "spll/4", "cpll/3", "spll/3",
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"spll/4", "spll/8", "cpll/4", "cpll/8"),
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UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
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"mpll/2", "spll/4", "mpll/3", "spll/3",
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"spll/4", "spll/8", "mpll/4", "mpll/8"),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */
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UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */
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UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
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UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */
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UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_LD11_SYS_CLK_EMMC(4),
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/* Index 5 reserved for eMMC PHY */
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UNIPHIER_LD20_SYS_CLK_SD,
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UNIPHIER_LD11_SYS_CLK_ETHER(6),
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UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
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/* GIO is always clock-enabled: no function for 0x210c bit5 */
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/*
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* clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
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* We do not use bit 15 here.
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*/
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UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
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UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
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UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
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UNIPHIER_LD11_SYS_CLK_AIO(40),
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UNIPHIER_LD11_SYS_CLK_EVEA(41),
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UNIPHIER_LD11_SYS_CLK_EXIV(42),
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/* CPU gears */
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UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
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UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
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UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
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UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
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"cpll/2", "spll/2", "cpll/3", "spll/3",
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"spll/4", "spll/8", "cpll/4", "cpll/8"),
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UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
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"cpll/2", "spll/2", "cpll/3", "spll/3",
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"spll/4", "spll/8", "cpll/4", "cpll/8"),
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UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
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"s2pll/2", "spll/2", "s2pll/3", "spll/3",
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"spll/4", "spll/8", "s2pll/4", "s2pll/8"),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
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UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
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UNIPHIER_LD20_SYS_CLK_SD,
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_LD11_SYS_CLK_EMMC(4),
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UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
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UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
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UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
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UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
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UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
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|
UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
|
|
UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
|
|
UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
|
|
/* CPU gears */
|
|
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
|
|
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
|
|
UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
|
|
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
|
|
"cpll/2", "spll/2", "cpll/3", "spll/3",
|
|
"spll/4", "spll/8", "cpll/4", "cpll/8"),
|
|
UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
|
|
"s2pll/2", "spll/2", "s2pll/3", "spll/3",
|
|
"spll/4", "spll/8", "s2pll/4", "s2pll/8"),
|
|
{ /* sentinel */ }
|
|
};
|