![Kay Sievers](/assets/img/avatar_default.png)
The sysdev.h file should not be needed by any in-kernel code, so remove the .h file from these random files that seem to still want to include it. The sysdev code will be going away soon, so this include needs to be removed no matter what. Cc: Jiandong Zheng <jdzheng@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Wan ZongShun <mcuos.com@gmail.com> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: "Venkatesh Pallipadi Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Matthew Garrett <mjg@redhat.com> Signed-off-by: Kay Sievers <kay.sievers@vrfy.org>
220 lines
5.1 KiB
C
220 lines
5.1 KiB
C
/* linux/arch/arm/plat-s5p/irq-eint.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P - IRQ EINT support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <asm/hardware/vic.h>
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#include <plat/regs-irqtype.h>
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#include <mach/map.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/gpio-cfg.h>
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#include <mach/regs-gpio.h>
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static inline void s5p_irq_eint_mask(struct irq_data *data)
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{
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u32 mask;
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mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
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mask |= eint_irq_to_bit(data->irq);
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__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
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}
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static void s5p_irq_eint_unmask(struct irq_data *data)
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{
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u32 mask;
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mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
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mask &= ~(eint_irq_to_bit(data->irq));
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__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
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}
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static inline void s5p_irq_eint_ack(struct irq_data *data)
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{
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__raw_writel(eint_irq_to_bit(data->irq),
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S5P_EINT_PEND(EINT_REG_NR(data->irq)));
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}
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static void s5p_irq_eint_maskack(struct irq_data *data)
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{
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/* compiler should in-line these */
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s5p_irq_eint_mask(data);
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s5p_irq_eint_ack(data);
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}
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static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
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{
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int offs = EINT_OFFSET(data->irq);
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S5P_IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -EINVAL;
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}
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shift = (offs & 0x7) * 4;
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mask = 0x7 << shift;
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ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
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ctrl &= ~mask;
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ctrl |= newvalue << shift;
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__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
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if ((0 <= offs) && (offs < 8))
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s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
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else if ((8 <= offs) && (offs < 16))
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s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
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else if ((16 <= offs) && (offs < 24))
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s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
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else if ((24 <= offs) && (offs < 32))
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s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
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else
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printk(KERN_ERR "No such irq number %d", offs);
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return 0;
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}
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static struct irq_chip s5p_irq_eint = {
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.name = "s5p-eint",
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.irq_mask = s5p_irq_eint_mask,
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.irq_unmask = s5p_irq_eint_unmask,
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.irq_mask_ack = s5p_irq_eint_maskack,
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.irq_ack = s5p_irq_eint_ack,
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.irq_set_type = s5p_irq_eint_set_type,
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#ifdef CONFIG_PM
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.irq_set_wake = s3c_irqext_wake,
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#endif
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};
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/* s5p_irq_demux_eint
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*
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* This function demuxes the IRQ from the group0 external interrupts,
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* from EINTs 16 to 31. It is designed to be inlined into the specific
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* handler s5p_irq_demux_eintX_Y.
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*
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* Each EINT pend/mask registers handle eight of them.
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*/
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static inline void s5p_irq_demux_eint(unsigned int start)
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{
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u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
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u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
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unsigned int irq;
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status &= ~mask;
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status &= 0xff;
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while (status) {
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irq = fls(status) - 1;
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generic_handle_irq(irq + start);
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status &= ~(1 << irq);
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}
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}
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static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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{
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s5p_irq_demux_eint(IRQ_EINT(16));
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s5p_irq_demux_eint(IRQ_EINT(24));
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}
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static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
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{
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void __iomem *base = irq_data_get_irq_chip_data(data);
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s5p_irq_eint_mask(data);
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writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
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}
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static void s5p_irq_vic_eint_unmask(struct irq_data *data)
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{
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void __iomem *base = irq_data_get_irq_chip_data(data);
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s5p_irq_eint_unmask(data);
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writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
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}
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static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
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{
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__raw_writel(eint_irq_to_bit(data->irq),
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S5P_EINT_PEND(EINT_REG_NR(data->irq)));
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}
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static void s5p_irq_vic_eint_maskack(struct irq_data *data)
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{
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s5p_irq_vic_eint_mask(data);
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s5p_irq_vic_eint_ack(data);
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}
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static struct irq_chip s5p_irq_vic_eint = {
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.name = "s5p_vic_eint",
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.irq_mask = s5p_irq_vic_eint_mask,
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.irq_unmask = s5p_irq_vic_eint_unmask,
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.irq_mask_ack = s5p_irq_vic_eint_maskack,
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.irq_ack = s5p_irq_vic_eint_ack,
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.irq_set_type = s5p_irq_eint_set_type,
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#ifdef CONFIG_PM
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.irq_set_wake = s3c_irqext_wake,
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#endif
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};
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int __init s5p_init_irq_eint(void)
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{
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int irq;
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for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
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irq_set_chip(irq, &s5p_irq_vic_eint);
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for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
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irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
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return 0;
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}
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arch_initcall(s5p_init_irq_eint);
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