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alistair23-linux/arch/x86/events
Stephane Eranian a803ea15b0 perf/x86/intel: Check PEBS status correctly
[ Upstream commit fc17db8aa4 ]

The kernel cannot disambiguate when 2+ PEBS counters overflow at the
same time. This is what the comment for this code suggests.  However,
I see the comparison is done with the unfiltered p->status which is a
copy of IA32_PERF_GLOBAL_STATUS at the time of the sample. This
register contains more than the PEBS counter overflow bits. It also
includes many other bits which could also be set.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201126110922.317681-2-namhyung@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-12-30 11:50:57 +01:00
..
amd perf/x86/amd/ibs: Fix raw sample data accumulation 2020-11-05 11:43:23 +01:00
intel perf/x86/intel: Check PEBS status correctly 2020-12-30 11:50:57 +01:00
Kconfig perf/x86/rapl: Move RAPL support to common x86 code 2020-07-16 08:16:32 +02:00
Makefile perf/x86/rapl: Fix RAPL config variable bug 2020-07-16 08:16:32 +02:00
core.c perf/x86/intel: Fix PT PMI handling 2020-01-12 12:21:36 +01:00
msr.c perf/x86/msr: Add Tremont support 2020-03-05 16:43:38 +01:00
perf_event.h perf/x86/amd: Constrain Large Increment per Cycle events 2020-02-24 08:36:52 +01:00
probe.c perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
probe.h perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
rapl.c perf/x86: fix sysfs type mismatches 2020-12-02 08:49:49 +01:00