b36ba30c8a
Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
38 lines
986 B
C
38 lines
986 B
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_RESET_H__
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#define __QCOM_CLK_RESET_H__
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#include <linux/reset-controller.h>
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struct qcom_reset_map {
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unsigned int reg;
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u8 bit;
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};
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struct regmap;
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struct qcom_reset_controller {
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const struct qcom_reset_map *reset_map;
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struct regmap *regmap;
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struct reset_controller_dev rcdev;
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};
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#define to_qcom_reset_controller(r) \
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container_of(r, struct qcom_reset_controller, rcdev);
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extern struct reset_control_ops qcom_reset_ops;
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#endif
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