46a57afdd7
Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/************************************************************************
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File : Clock H/w specific Information
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Author: Pankaj Dev <pankaj.dev@st.com>
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Copyright (C) 2014 STMicroelectronics
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************************************************************************/
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#ifndef __CLKGEN_INFO_H
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#define __CLKGEN_INFO_H
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extern spinlock_t clkgen_a9_lock;
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struct clkgen_field {
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unsigned int offset;
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unsigned int mask;
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unsigned int shift;
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};
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static inline unsigned long clkgen_read(void __iomem *base,
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struct clkgen_field *field)
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{
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return (readl(base + field->offset) >> field->shift) & field->mask;
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}
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static inline void clkgen_write(void __iomem *base, struct clkgen_field *field,
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unsigned long val)
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{
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writel((readl(base + field->offset) &
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~(field->mask << field->shift)) | (val << field->shift),
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base + field->offset);
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return;
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}
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#define CLKGEN_FIELD(_offset, _mask, _shift) { \
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.offset = _offset, \
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.mask = _mask, \
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.shift = _shift, \
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}
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#define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \
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&pll->data->field)
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#define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
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&pll->data->field, val)
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#endif /*__CLKGEN_INFO_H*/
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