4599dd2c92
Add SPDIF/I2S divider clock method for zx296702 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
42 lines
1,018 B
C
42 lines
1,018 B
C
/*
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* Copyright 2015 Linaro Ltd.
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* Copyright (C) 2014 ZTE Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ZTE_CLK_H
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#define __ZTE_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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struct zx_pll_config {
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unsigned long rate;
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u32 cfg0;
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u32 cfg1;
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};
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struct clk_zx_pll {
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struct clk_hw hw;
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void __iomem *reg_base;
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const struct zx_pll_config *lookup_table; /* order by rate asc */
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int count;
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spinlock_t *lock;
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};
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struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg_base,
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const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
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struct clk_zx_audio {
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struct clk_hw hw;
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void __iomem *reg_base;
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};
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struct clk *clk_register_zx_audio(const char *name,
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const char * const parent_name,
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unsigned long flags, void __iomem *reg_base);
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#endif
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