76148df19c
GRU Message queue instructions are used to deliver messages to other SSIs within the numalink domain. In most cases, a single GRU mesq instruction will deliver both the message AND an interrupt to notify the other SSI that a messsage is present. In some cases, however, the interrupt must be sent explicitly. To improve resilency, the GRU driver should send these explicit interrupts using the GRU to write the remote chipset register. Current code sends the interrupt using a cpu instruction to write the chipset register. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
736 lines
21 KiB
C
736 lines
21 KiB
C
/*
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* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __GRU_INSTRUCTIONS_H__
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#define __GRU_INSTRUCTIONS_H__
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extern int gru_check_status_proc(void *cb);
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extern int gru_wait_proc(void *cb);
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extern void gru_wait_abort_proc(void *cb);
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/*
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* Architecture dependent functions
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*/
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#if defined(CONFIG_IA64)
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#include <linux/compiler.h>
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#include <asm/intrinsics.h>
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#define __flush_cache(p) ia64_fc((unsigned long)p)
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/* Use volatile on IA64 to ensure ordering via st4.rel */
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#define gru_ordered_store_ulong(p, v) \
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do { \
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barrier(); \
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*((volatile unsigned long *)(p)) = v; /* force st.rel */ \
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} while (0)
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#elif defined(CONFIG_X86_64)
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#define __flush_cache(p) clflush(p)
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#define gru_ordered_store_ulong(p, v) \
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do { \
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barrier(); \
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*(unsigned long *)p = v; \
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} while (0)
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#else
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#error "Unsupported architecture"
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#endif
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/*
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* Control block status and exception codes
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*/
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#define CBS_IDLE 0
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#define CBS_EXCEPTION 1
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#define CBS_ACTIVE 2
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#define CBS_CALL_OS 3
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/* CB substatus bitmasks */
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#define CBSS_MSG_QUEUE_MASK 7
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#define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8
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/* CB substatus message queue values (low 3 bits of substatus) */
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#define CBSS_NO_ERROR 0
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#define CBSS_LB_OVERFLOWED 1
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#define CBSS_QLIMIT_REACHED 2
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#define CBSS_PAGE_OVERFLOW 3
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#define CBSS_AMO_NACKED 4
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#define CBSS_PUT_NACKED 5
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/*
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* Structure used to fetch exception detail for CBs that terminate with
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* CBS_EXCEPTION
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*/
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struct control_block_extended_exc_detail {
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unsigned long cb;
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int opc;
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int ecause;
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int exopc;
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long exceptdet0;
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int exceptdet1;
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int cbrstate;
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int cbrexecstatus;
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};
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/*
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* Instruction formats
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*/
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/*
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* Generic instruction format.
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* This definition has precise bit field definitions.
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*/
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struct gru_instruction_bits {
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/* DW 0 - low */
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unsigned int icmd: 1;
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unsigned char ima: 3; /* CB_DelRep, unmapped mode */
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unsigned char reserved0: 4;
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unsigned int xtype: 3;
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unsigned int iaa0: 2;
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unsigned int iaa1: 2;
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unsigned char reserved1: 1;
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unsigned char opc: 8; /* opcode */
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unsigned char exopc: 8; /* extended opcode */
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/* DW 0 - high */
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unsigned int idef2: 22; /* TRi0 */
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unsigned char reserved2: 2;
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unsigned char istatus: 2;
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unsigned char isubstatus:4;
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unsigned char reserved3: 1;
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unsigned char tlb_fault_color: 1;
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/* DW 1 */
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unsigned long idef4; /* 42 bits: TRi1, BufSize */
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/* DW 2-6 */
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unsigned long idef1; /* BAddr0 */
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unsigned long idef5; /* Nelem */
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unsigned long idef6; /* Stride, Operand1 */
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unsigned long idef3; /* BAddr1, Value, Operand2 */
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unsigned long reserved4;
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/* DW 7 */
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unsigned long avalue; /* AValue */
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};
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/*
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* Generic instruction with friendlier names. This format is used
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* for inline instructions.
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*/
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struct gru_instruction {
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/* DW 0 */
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union {
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unsigned long op64; /* icmd,xtype,iaa0,ima,opc,tri0 */
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struct {
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unsigned int op32;
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unsigned int tri0;
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};
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};
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unsigned long tri1_bufsize; /* DW 1 */
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unsigned long baddr0; /* DW 2 */
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unsigned long nelem; /* DW 3 */
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unsigned long op1_stride; /* DW 4 */
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unsigned long op2_value_baddr1; /* DW 5 */
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unsigned long reserved0; /* DW 6 */
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unsigned long avalue; /* DW 7 */
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};
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/* Some shifts and masks for the low 64 bits of a GRU command */
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#define GRU_CB_ICMD_SHFT 0
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#define GRU_CB_ICMD_MASK 0x1
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#define GRU_CB_XTYPE_SHFT 8
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#define GRU_CB_XTYPE_MASK 0x7
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#define GRU_CB_IAA0_SHFT 11
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#define GRU_CB_IAA0_MASK 0x3
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#define GRU_CB_IAA1_SHFT 13
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#define GRU_CB_IAA1_MASK 0x3
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#define GRU_CB_IMA_SHFT 1
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#define GRU_CB_IMA_MASK 0x3
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#define GRU_CB_OPC_SHFT 16
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#define GRU_CB_OPC_MASK 0xff
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#define GRU_CB_EXOPC_SHFT 24
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#define GRU_CB_EXOPC_MASK 0xff
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#define GRU_IDEF2_SHFT 32
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#define GRU_IDEF2_MASK 0x3ffff
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#define GRU_ISTATUS_SHFT 56
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#define GRU_ISTATUS_MASK 0x3
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/* GRU instruction opcodes (opc field) */
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#define OP_NOP 0x00
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#define OP_BCOPY 0x01
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#define OP_VLOAD 0x02
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#define OP_IVLOAD 0x03
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#define OP_VSTORE 0x04
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#define OP_IVSTORE 0x05
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#define OP_VSET 0x06
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#define OP_IVSET 0x07
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#define OP_MESQ 0x08
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#define OP_GAMXR 0x09
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#define OP_GAMIR 0x0a
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#define OP_GAMIRR 0x0b
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#define OP_GAMER 0x0c
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#define OP_GAMERR 0x0d
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#define OP_BSTORE 0x0e
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#define OP_VFLUSH 0x0f
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/* Extended opcodes values (exopc field) */
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/* GAMIR - AMOs with implicit operands */
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#define EOP_IR_FETCH 0x01 /* Plain fetch of memory */
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#define EOP_IR_CLR 0x02 /* Fetch and clear */
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#define EOP_IR_INC 0x05 /* Fetch and increment */
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#define EOP_IR_DEC 0x07 /* Fetch and decrement */
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#define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */
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#define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */
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/* GAMIRR - Registered AMOs with implicit operands */
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#define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */
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#define EOP_IRR_CLR 0x02 /* Registered fetch and clear */
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#define EOP_IRR_INC 0x05 /* Registered fetch and increment */
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#define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */
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#define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/
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/* GAMER - AMOs with explicit operands */
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#define EOP_ER_SWAP 0x00 /* Exchange argument and memory */
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#define EOP_ER_OR 0x01 /* Logical OR with memory */
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#define EOP_ER_AND 0x02 /* Logical AND with memory */
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#define EOP_ER_XOR 0x03 /* Logical XOR with memory */
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#define EOP_ER_ADD 0x04 /* Add value to memory */
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#define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/
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#define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */
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/* GAMERR - Registered AMOs with explicit operands */
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#define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */
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#define EOP_ERR_OR 0x01 /* Logical OR with memory */
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#define EOP_ERR_AND 0x02 /* Logical AND with memory */
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#define EOP_ERR_XOR 0x03 /* Logical XOR with memory */
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#define EOP_ERR_ADD 0x04 /* Add value to memory */
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#define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/
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#define EOP_ERR_EPOLL 0x09 /* Poll for equality */
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#define EOP_ERR_NPOLL 0x0a /* Poll for inequality */
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/* GAMXR - SGI Arithmetic unit */
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#define EOP_XR_CSWAP 0x0b /* Masked compare exchange */
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/* Transfer types (xtype field) */
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#define XTYPE_B 0x0 /* byte */
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#define XTYPE_S 0x1 /* short (2-byte) */
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#define XTYPE_W 0x2 /* word (4-byte) */
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#define XTYPE_DW 0x3 /* doubleword (8-byte) */
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#define XTYPE_CL 0x6 /* cacheline (64-byte) */
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/* Instruction access attributes (iaa0, iaa1 fields) */
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#define IAA_RAM 0x0 /* normal cached RAM access */
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#define IAA_NCRAM 0x2 /* noncoherent RAM access */
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#define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */
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#define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */
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/* Instruction mode attributes (ima field) */
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#define IMA_MAPPED 0x0 /* Virtual mode */
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#define IMA_CB_DELAY 0x1 /* hold read responses until status changes */
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#define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */
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#define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */
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/* CBE ecause bits */
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#define CBE_CAUSE_RI (1 << 0)
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#define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1)
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#define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2)
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#define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3)
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#define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4)
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#define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5)
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#define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6)
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#define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7)
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#define CBE_CAUSE_TLBHW_ERROR (1 << 8)
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#define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9)
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#define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10)
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#define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11)
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#define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12)
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#define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13)
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#define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14)
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#define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15)
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#define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 16)
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#define CBE_CAUSE_RA_RESPONSE_DATA_ERROR (1 << 17)
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#define CBE_CAUSE_HA_RESPONSE_DATA_ERROR (1 << 18)
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#define CBE_CAUSE_FORCED_ERROR (1 << 19)
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/* CBE cbrexecstatus bits */
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#define CBR_EXS_ABORT_OCC_BIT 0
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#define CBR_EXS_INT_OCC_BIT 1
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#define CBR_EXS_PENDING_BIT 2
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#define CBR_EXS_QUEUED_BIT 3
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#define CBR_EXS_TLB_INVAL_BIT 4
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#define CBR_EXS_EXCEPTION_BIT 5
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#define CBR_EXS_CB_INT_PENDING_BIT 6
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#define CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT)
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#define CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT)
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#define CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT)
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#define CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT)
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#define CBR_EXS_TLB_INVAL (1 << CBR_EXS_TLB_INVAL_BIT)
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#define CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT)
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#define CBR_EXS_CB_INT_PENDING (1 << CBR_EXS_CB_INT_PENDING_BIT)
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/*
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* Exceptions are retried for the following cases. If any OTHER bits are set
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* in ecause, the exception is not retryable.
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*/
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#define EXCEPTION_RETRY_BITS (CBE_CAUSE_EXECUTION_HW_ERROR | \
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CBE_CAUSE_TLBHW_ERROR | \
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CBE_CAUSE_RA_REQUEST_TIMEOUT | \
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CBE_CAUSE_RA_RESPONSE_NON_FATAL | \
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CBE_CAUSE_HA_RESPONSE_NON_FATAL | \
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CBE_CAUSE_RA_RESPONSE_DATA_ERROR | \
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CBE_CAUSE_HA_RESPONSE_DATA_ERROR \
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)
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/* Message queue head structure */
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union gru_mesqhead {
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unsigned long val;
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struct {
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unsigned int head;
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unsigned int limit;
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};
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};
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/* Generate the low word of a GRU instruction */
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static inline unsigned long
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__opdword(unsigned char opcode, unsigned char exopc, unsigned char xtype,
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unsigned char iaa0, unsigned char iaa1,
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unsigned long idef2, unsigned char ima)
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{
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return (1 << GRU_CB_ICMD_SHFT) |
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((unsigned long)CBS_ACTIVE << GRU_ISTATUS_SHFT) |
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(idef2<< GRU_IDEF2_SHFT) |
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(iaa0 << GRU_CB_IAA0_SHFT) |
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(iaa1 << GRU_CB_IAA1_SHFT) |
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(ima << GRU_CB_IMA_SHFT) |
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(xtype << GRU_CB_XTYPE_SHFT) |
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(opcode << GRU_CB_OPC_SHFT) |
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(exopc << GRU_CB_EXOPC_SHFT);
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}
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/*
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* Architecture specific intrinsics
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*/
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static inline void gru_flush_cache(void *p)
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{
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__flush_cache(p);
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}
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/*
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* Store the lower 64 bits of the command including the "start" bit. Then
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* start the instruction executing.
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*/
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static inline void gru_start_instruction(struct gru_instruction *ins, unsigned long op64)
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{
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gru_ordered_store_ulong(ins, op64);
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mb();
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gru_flush_cache(ins);
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}
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/* Convert "hints" to IMA */
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#define CB_IMA(h) ((h) | IMA_UNMAPPED)
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/* Convert data segment cache line index into TRI0 / TRI1 value */
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#define GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES)
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/* Inline functions for GRU instructions.
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* Note:
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* - nelem and stride are in elements
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* - tri0/tri1 is in bytes for the beginning of the data segment.
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*/
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static inline void gru_vload_phys(void *cb, unsigned long gpa,
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unsigned int tri0, int iaa, unsigned long hints)
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{
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struct gru_instruction *ins = (struct gru_instruction *)cb;
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ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62);
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ins->nelem = 1;
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ins->op1_stride = 1;
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gru_start_instruction(ins, __opdword(OP_VLOAD, 0, XTYPE_DW, iaa, 0,
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(unsigned long)tri0, CB_IMA(hints)));
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}
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static inline void gru_vstore_phys(void *cb, unsigned long gpa,
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unsigned int tri0, int iaa, unsigned long hints)
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{
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struct gru_instruction *ins = (struct gru_instruction *)cb;
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ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62);
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ins->nelem = 1;
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ins->op1_stride = 1;
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gru_start_instruction(ins, __opdword(OP_VSTORE, 0, XTYPE_DW, iaa, 0,
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(unsigned long)tri0, CB_IMA(hints)));
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}
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static inline void gru_vload(void *cb, unsigned long mem_addr,
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unsigned int tri0, unsigned char xtype, unsigned long nelem,
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unsigned long stride, unsigned long hints)
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{
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struct gru_instruction *ins = (struct gru_instruction *)cb;
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ins->baddr0 = (long)mem_addr;
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ins->nelem = nelem;
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ins->op1_stride = stride;
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gru_start_instruction(ins, __opdword(OP_VLOAD, 0, xtype, IAA_RAM, 0,
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(unsigned long)tri0, CB_IMA(hints)));
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}
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static inline void gru_vstore(void *cb, unsigned long mem_addr,
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unsigned int tri0, unsigned char xtype, unsigned long nelem,
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unsigned long stride, unsigned long hints)
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{
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struct gru_instruction *ins = (void *)cb;
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ins->baddr0 = (long)mem_addr;
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ins->nelem = nelem;
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ins->op1_stride = stride;
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gru_start_instruction(ins, __opdword(OP_VSTORE, 0, xtype, IAA_RAM, 0,
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tri0, CB_IMA(hints)));
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}
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static inline void gru_ivload(void *cb, unsigned long mem_addr,
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unsigned int tri0, unsigned int tri1, unsigned char xtype,
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unsigned long nelem, unsigned long hints)
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{
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struct gru_instruction *ins = (void *)cb;
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ins->baddr0 = (long)mem_addr;
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ins->nelem = nelem;
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ins->tri1_bufsize = tri1;
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gru_start_instruction(ins, __opdword(OP_IVLOAD, 0, xtype, IAA_RAM, 0,
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tri0, CB_IMA(hints)));
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}
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static inline void gru_ivstore(void *cb, unsigned long mem_addr,
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unsigned int tri0, unsigned int tri1,
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unsigned char xtype, unsigned long nelem, unsigned long hints)
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{
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struct gru_instruction *ins = (void *)cb;
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ins->baddr0 = (long)mem_addr;
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ins->nelem = nelem;
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ins->tri1_bufsize = tri1;
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gru_start_instruction(ins, __opdword(OP_IVSTORE, 0, xtype, IAA_RAM, 0,
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tri0, CB_IMA(hints)));
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}
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static inline void gru_vset(void *cb, unsigned long mem_addr,
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unsigned long value, unsigned char xtype, unsigned long nelem,
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unsigned long stride, unsigned long hints)
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{
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struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)mem_addr;
|
|
ins->op2_value_baddr1 = value;
|
|
ins->nelem = nelem;
|
|
ins->op1_stride = stride;
|
|
gru_start_instruction(ins, __opdword(OP_VSET, 0, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_ivset(void *cb, unsigned long mem_addr,
|
|
unsigned int tri1, unsigned long value, unsigned char xtype,
|
|
unsigned long nelem, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)mem_addr;
|
|
ins->op2_value_baddr1 = value;
|
|
ins->nelem = nelem;
|
|
ins->tri1_bufsize = tri1;
|
|
gru_start_instruction(ins, __opdword(OP_IVSET, 0, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_vflush(void *cb, unsigned long mem_addr,
|
|
unsigned long nelem, unsigned char xtype, unsigned long stride,
|
|
unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)mem_addr;
|
|
ins->op1_stride = stride;
|
|
ins->nelem = nelem;
|
|
gru_start_instruction(ins, __opdword(OP_VFLUSH, 0, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_nop(void *cb, int hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
gru_start_instruction(ins, __opdword(OP_NOP, 0, 0, 0, 0, 0, CB_IMA(hints)));
|
|
}
|
|
|
|
|
|
static inline void gru_bcopy(void *cb, const unsigned long src,
|
|
unsigned long dest,
|
|
unsigned int tri0, unsigned int xtype, unsigned long nelem,
|
|
unsigned int bufsize, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
ins->op2_value_baddr1 = (long)dest;
|
|
ins->nelem = nelem;
|
|
ins->tri1_bufsize = bufsize;
|
|
gru_start_instruction(ins, __opdword(OP_BCOPY, 0, xtype, IAA_RAM,
|
|
IAA_RAM, tri0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_bstore(void *cb, const unsigned long src,
|
|
unsigned long dest, unsigned int tri0, unsigned int xtype,
|
|
unsigned long nelem, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
ins->op2_value_baddr1 = (long)dest;
|
|
ins->nelem = nelem;
|
|
gru_start_instruction(ins, __opdword(OP_BSTORE, 0, xtype, 0, IAA_RAM,
|
|
tri0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_gamir(void *cb, int exopc, unsigned long src,
|
|
unsigned int xtype, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
gru_start_instruction(ins, __opdword(OP_GAMIR, exopc, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_gamirr(void *cb, int exopc, unsigned long src,
|
|
unsigned int xtype, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
gru_start_instruction(ins, __opdword(OP_GAMIRR, exopc, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_gamer(void *cb, int exopc, unsigned long src,
|
|
unsigned int xtype,
|
|
unsigned long operand1, unsigned long operand2,
|
|
unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
ins->op1_stride = operand1;
|
|
ins->op2_value_baddr1 = operand2;
|
|
gru_start_instruction(ins, __opdword(OP_GAMER, exopc, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_gamerr(void *cb, int exopc, unsigned long src,
|
|
unsigned int xtype, unsigned long operand1,
|
|
unsigned long operand2, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
ins->op1_stride = operand1;
|
|
ins->op2_value_baddr1 = operand2;
|
|
gru_start_instruction(ins, __opdword(OP_GAMERR, exopc, xtype, IAA_RAM, 0,
|
|
0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_gamxr(void *cb, unsigned long src,
|
|
unsigned int tri0, unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)src;
|
|
ins->nelem = 4;
|
|
gru_start_instruction(ins, __opdword(OP_GAMXR, EOP_XR_CSWAP, XTYPE_DW,
|
|
IAA_RAM, 0, 0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline void gru_mesq(void *cb, unsigned long queue,
|
|
unsigned long tri0, unsigned long nelem,
|
|
unsigned long hints)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
ins->baddr0 = (long)queue;
|
|
ins->nelem = nelem;
|
|
gru_start_instruction(ins, __opdword(OP_MESQ, 0, XTYPE_CL, IAA_RAM, 0,
|
|
tri0, CB_IMA(hints)));
|
|
}
|
|
|
|
static inline unsigned long gru_get_amo_value(void *cb)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
return ins->avalue;
|
|
}
|
|
|
|
static inline int gru_get_amo_value_head(void *cb)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
return ins->avalue & 0xffffffff;
|
|
}
|
|
|
|
static inline int gru_get_amo_value_limit(void *cb)
|
|
{
|
|
struct gru_instruction *ins = (void *)cb;
|
|
|
|
return ins->avalue >> 32;
|
|
}
|
|
|
|
static inline union gru_mesqhead gru_mesq_head(int head, int limit)
|
|
{
|
|
union gru_mesqhead mqh;
|
|
|
|
mqh.head = head;
|
|
mqh.limit = limit;
|
|
return mqh;
|
|
}
|
|
|
|
/*
|
|
* Get struct control_block_extended_exc_detail for CB.
|
|
*/
|
|
extern int gru_get_cb_exception_detail(void *cb,
|
|
struct control_block_extended_exc_detail *excdet);
|
|
|
|
#define GRU_EXC_STR_SIZE 256
|
|
|
|
|
|
/*
|
|
* Control block definition for checking status
|
|
*/
|
|
struct gru_control_block_status {
|
|
unsigned int icmd :1;
|
|
unsigned int ima :3;
|
|
unsigned int reserved0 :4;
|
|
unsigned int unused1 :24;
|
|
unsigned int unused2 :24;
|
|
unsigned int istatus :2;
|
|
unsigned int isubstatus :4;
|
|
unsigned int unused3 :2;
|
|
};
|
|
|
|
/* Get CB status */
|
|
static inline int gru_get_cb_status(void *cb)
|
|
{
|
|
struct gru_control_block_status *cbs = (void *)cb;
|
|
|
|
return cbs->istatus;
|
|
}
|
|
|
|
/* Get CB message queue substatus */
|
|
static inline int gru_get_cb_message_queue_substatus(void *cb)
|
|
{
|
|
struct gru_control_block_status *cbs = (void *)cb;
|
|
|
|
return cbs->isubstatus & CBSS_MSG_QUEUE_MASK;
|
|
}
|
|
|
|
/* Get CB substatus */
|
|
static inline int gru_get_cb_substatus(void *cb)
|
|
{
|
|
struct gru_control_block_status *cbs = (void *)cb;
|
|
|
|
return cbs->isubstatus;
|
|
}
|
|
|
|
/*
|
|
* User interface to check an instruction status. UPM and exceptions
|
|
* are handled automatically. However, this function does NOT wait
|
|
* for an active instruction to complete.
|
|
*
|
|
*/
|
|
static inline int gru_check_status(void *cb)
|
|
{
|
|
struct gru_control_block_status *cbs = (void *)cb;
|
|
int ret;
|
|
|
|
ret = cbs->istatus;
|
|
if (ret != CBS_ACTIVE)
|
|
ret = gru_check_status_proc(cb);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* User interface (via inline function) to wait for an instruction
|
|
* to complete. Completion status (IDLE or EXCEPTION is returned
|
|
* to the user. Exception due to hardware errors are automatically
|
|
* retried before returning an exception.
|
|
*
|
|
*/
|
|
static inline int gru_wait(void *cb)
|
|
{
|
|
return gru_wait_proc(cb);
|
|
}
|
|
|
|
/*
|
|
* Wait for CB to complete. Aborts program if error. (Note: error does NOT
|
|
* mean TLB mis - only fatal errors such as memory parity error or user
|
|
* bugs will cause termination.
|
|
*/
|
|
static inline void gru_wait_abort(void *cb)
|
|
{
|
|
gru_wait_abort_proc(cb);
|
|
}
|
|
|
|
/*
|
|
* Get a pointer to the start of a gseg
|
|
* p - Any valid pointer within the gseg
|
|
*/
|
|
static inline void *gru_get_gseg_pointer (void *p)
|
|
{
|
|
return (void *)((unsigned long)p & ~(GRU_GSEG_PAGESIZE - 1));
|
|
}
|
|
|
|
/*
|
|
* Get a pointer to a control block
|
|
* gseg - GSeg address returned from gru_get_thread_gru_segment()
|
|
* index - index of desired CB
|
|
*/
|
|
static inline void *gru_get_cb_pointer(void *gseg,
|
|
int index)
|
|
{
|
|
return gseg + GRU_CB_BASE + index * GRU_HANDLE_STRIDE;
|
|
}
|
|
|
|
/*
|
|
* Get a pointer to a cacheline in the data segment portion of a GSeg
|
|
* gseg - GSeg address returned from gru_get_thread_gru_segment()
|
|
* index - index of desired cache line
|
|
*/
|
|
static inline void *gru_get_data_pointer(void *gseg, int index)
|
|
{
|
|
return gseg + GRU_DS_BASE + index * GRU_CACHE_LINE_BYTES;
|
|
}
|
|
|
|
/*
|
|
* Convert a vaddr into the tri index within the GSEG
|
|
* vaddr - virtual address of within gseg
|
|
*/
|
|
static inline int gru_get_tri(void *vaddr)
|
|
{
|
|
return ((unsigned long)vaddr & (GRU_GSEG_PAGESIZE - 1)) - GRU_DS_BASE;
|
|
}
|
|
#endif /* __GRU_INSTRUCTIONS_H__ */
|